MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 258

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

11.4.1.2 Status Register
11.4.1.3 Data Register
11.4.2 SCI Pins
11.4.3 SCI Operation
11.4.3.1 Definition of Terms
11-26
MOTOROLA
SCSR contains flags that show SCI operating conditions. These flags are cleared
either by SCI hardware or by reading SCSR, then reading or writing SCDR. A long-
word read can consecutively access both SCSR and SCDR. This action clears
receiver status flag bits that were set at the time of the read, but does not clear TDRE
or TC flags.
If an internal SCI signal for setting a status bit comes after reading the asserted status
bits, but before reading or writing SCDR, the newly set status bit is not cleared. SCSR
must be read again with the bit set, and SCDR must be read or written before the
status bit is cleared.
Reading either byte of SCSR causes all 16 bits to be accessed, and any status bit
already set in either byte is cleared on a subsequent read or write of SCDR.
SCDR contains two data registers at the same address. The receive data register
(RDR) is a read-only register that contains data received by the SCI. Data enters the
receive serial shifter and is transferred to RDR. The transmit data register (TDR) is a
write-only register that contains data to be transmitted. Data is first written to TDR,
then transferred to the transmit serial shifter, where additional format bits are added
before transmission. R[7:0]/T[7:0] contain either the first eight data bits received when
SCDR is read, or the first eight data bits to be transmitted when SCDR is written. R8/
T8 are used when the SCI is configured for 9-bit operation. When the SCI is configured
for 8-bit operation, they have no meaning or effect.
Two unidirectional pins, TXD (transmit data) and RXD (receive data), are associated
with the SCI. TXD can be used by the SCI or for general-purpose I/O. TXD function is
controlled by PQSPA7 in the port QS pin assignment register (PQSPAR) and TE in
SCI control register 1 (SCCR1). The receive data (RXD) pin is dedicated to the SCI.
The SCI can operate in polled or interrupt-driven mode. Status flags in SCSR reflect
SCI conditions regardless of the operating mode chosen. The TIE, TCIE, RIE, and ILIE
bits in SCCR1 enable interrupts for the conditions indicated by the TDRE, TC, RDRF,
and IDLE bits in SCSR, respectively.
• Bit-Time — The time required to transmit or receive one bit of data, which is equal
• Start Bit — One bit-time of logic zero that indicates the beginning of a data frame.
• Stop Bit— One bit-time of logic one that indicates the end of a data frame.
to one cycle of the baud frequency.
A start bit must begin with a one-to-zero transition and be preceded by at least
three receive time samples of logic one.
QUEUED SERIAL MODULE
MC68HC16Y3/916Y3
USER’S MANUAL