MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 211

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

10.2.2 Analog Reference Pins
10.2.3 Analog Supply Pins
10.3 Programmer’s Model
10.4 ADC Bus Interface Unit
10.5 Special Operating Modes
MC68HC16Y3/916Y3
USER’S MANUAL
Separate high (V
alog reference pins. The pins permit connection of regulated and filtered supplies that
allow the ADC to achieve its highest degree of accuracy.
Pins V
Other circuitry in the ADC is powered from the digital power bus (pins V
Dedicated analog power supplies are necessary to isolate sensitive ADC circuitry from
noise on the digital power bus.
The ADC module is mapped into 32 words of address space. Five words are control/
status registers, one word is digital port data, and 24 words provide access to the re-
sults of AD conversion (eight addresses for each type of converted data). Two words
are reserved for expansion.
The ADC module base address is determined by the value of the MM bit in the single-
chip integration module configuration register (SCIMCR). The base address is normal-
ly $FFF700.
Internally, the ADC has both a differential data bus and a buffered IMB data bus. Reg-
isters not directly associated with conversion functions, such as the module configu-
ration register, the module test register, and the port data register, reside on the
buffered bus, while conversion registers and result registers reside on the differential
bus.
Registers that reside on the buffered bus are updated immediately when written. How-
ever, writes to ADC control registers abort any conversion in progress.
The ADC is designed to act as a slave device on the intermodule bus. The ADC bus
interface unit (ABIU) provides IMB bus cycle termination and synchronizes internal
ADC signals with IMB signals. The ABIU also manages data bus routing to accommo-
date the three conversion data formats, and controls the interface to the module differ-
ential data bus.
Low-power stop mode and freeze mode are ADC operating modes associated with as-
sertion of IMB signals by other microcontroller modules or by external sources. These
modes are controlled by the values of bits in the ADC module configuration register
(ADCMCR).
DDA
and V
RH
SSA
) and low (V
supply power to analog circuitry associated with the RC DAC.
ANALOG-TO-DIGITAL CONVERTER
RL
) analog reference voltages are connected to the an-
DDI
MOTOROLA
and V
SSI
10-3
).