MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 401

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

IPL[2:0] — Interrupt Priority Level
AVEC — Autovector Enable
D.2.28 Master Shift Registers
TSTMSRA — Test Module Master Shift Register A
MC68HC16Y3/916Y3
USER’S MANUAL
When SPACE[1:0] is set for CPU space (%00), chip-select logic can be used as an
interrupt acknowledge strobe for an external device. During an interrupt acknowledge
cycle, the interrupt priority level is driven on address lines ADDR[3:1] is then compared
to the value in IPL[2:0]. If the values match, an interrupt acknowledge strobe will be
generated on the particular chip-select pin, provided other option register conditions
are met. Table D-17 shows IPL[2:0] field encoding.
This field selects one of two methods of acquiring an interrupt vector during an
interrupt acknowledge cycle. This field is not applicable when SPACE[1:0] = %00.
If the chip select is configured to trigger on an interrupt acknowledge cycle
(SPACE[1:0] = %00) and the AVEC field is set to one, the chip-select automatically
generates AVEC and completes the interrupt acknowledge cycle. Otherwise, the
vector must be supplied by the requesting external device to complete the IACK read
cycle.
Used for factory test only.
0 = External interrupt vector enabled
1 = Autovector enabled
NOTES:
Table D-17 Interrupt Priority Level Field Encoding
1. Any level means that chip-select is asserted regardless of the level of the
IPL[2:0]
000
001
010
011
100
101
110
111
interrupt acknowledge cycle.
Table D-16 Address Space Bit Encodings
SPACE[1:0]
00
01
10
11
REGISTER SUMMARY
Interrupt Priority Level
Supervisor/User Space
Supervisor Space
Address Space
Any Level
CPU Space
User Space
1
2
3
4
5
6
7
1
$YFFA30
MOTOROLA
D-23