MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 236

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

11.2.2 QSM Pin Control Registers
11-4
MOTOROLA
At reset, INTV[7:0] is initialized to $0F, the uninitialized interrupt vector number. To en-
able interrupt-driven serial communication, a user-defined vector number must be writ-
ten to QIVR, and interrupt handler routines must be located at the addresses pointed
to by the corresponding vector. Writes to INTV0 have no effect. Reads of INTV0 return
a value of one.
Refer to SECTION 4 CENTRAL PROCESSOR UNIT and SECTION 5 SINGLE-CHIP
INTEGRATION MODULE 2 for more information about exceptions and interrupts.
The QSM uses nine pins. Eight of the pins can be used for serial communication or for
parallel I/O. Clearing a bit in the port QS pin assignment register (PQSPAR) assigns
the corresponding pin to general-purpose I/O; setting a bit assigns the pin to the QSPI.
PQSPAR does not affect operation of the SCI.
The port QS data direction register (DDRQS) determines whether pins are inputs or
outputs. Clearing a bit makes the corresponding pin an input; setting a bit makes the
pin an output. DDRQS affects both QSPI function and I/O function. DDQS7 deter-
mines the direction of the TXD pin only when the SCI transmitter is disabled. When the
SCI transmitter is enabled, the TXD pin is an output.
The port QS data register (PORTQS) latches I/O data. PORTQS writes drive pins de-
fined as outputs. PORTQS reads return data present on the pins. To avoid driving un-
defined data, first write PORTQS, then configure DDRQS.
PQSPAR and DDRQS are 8-bit registers located at the same word address. Table 11-
1 is a summary of QSM pin functions.
QUEUED SERIAL MODULE
MC68HC16Y3/916Y3
USER’S MANUAL