MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 215

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

10.7.3 Sample Time
10.7.4 Resolution
10.7.5 Conversion Control Logic
MC68HC16Y3/916Y3
USER’S MANUAL
ADC clock speed must be between 0.5 MHz and 2.1 MHz. The reset value of the PRS
field is %00011, which divides a nominal 16.78 MHz system clock by eight, yielding
maximum ADC clock frequency. There are a minimum of four IMB clock cycles for
each ADC clock cycle.
The first two portions of all sample periods require four ADC clock cycles. During the
third portion of a sample period, the selected channel is connected directly to the RC
DAC array for a specified number of clock cycles. The value of the STS field in
ADCTL0 determines the number of cycles. Refer to Table 10-4. The number of clock
cycles required for a sample period is the value specified by STS plus four. Sample
time is determined by PRS value.
ADC resolution can be either eight or ten bits. Resolution is determined by the state of
the RES10 bit in ADCTL0. Both 8-bit and 10-bit conversion results are automatically
aligned in the result registers.
Analog-to-digital conversions are performed in sequences. Sequences are initiated by
any write to ADCTL1. If a conversion sequence is already in progress, a write to either
control register will abort it and reset the SCF and CCF flags in the A/D status register.
There are eight conversion modes. Conversion mode is determined by ADCTL1 con-
trol bits. Each conversion mode affects the bits in status register ADSTAT differently.
Result storage differs from mode to mode.
PRS[4:0]
%00000
%00001
%00010
%00011
%11101
%11110
%11111
STS[1:0]
Table 10-4 Sample Time Selection
00
01
10
11
ANALOG-TO-DIGITAL CONVERTER
System Clock/60
System Clock/62
System Clock/64
System Clock/4
System Clock/6
System Clock/8
Table 10-3 Prescaler Output
ADC Clock
Reserved
System Clock
16 ADC Clock Periods
2 ADC Clock Periods
4 ADC Clock Periods
8 ADC Clock Periods
Minimum
30.0 MHz
31.0 MHz
32.0 MHz
2.0 MHz
3.0 MHz
4.0 MHz
Sample Time
—
System Clock
Maximum
12.6 MHz
16.8 MHz
8.4 MHz
—
—
—
—
MOTOROLA
10-7