MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 468

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

FRZ[1:0] — FREEZE Assertion Response
CCL — Channel Conditions Latch
BP, BC, BH, BL, BM, and BT — Breakpoint Enable Bits
D.10.4 Development Support Status Register
DSSR — Development Support Status Register
BKPT — Breakpoint Asserted Flag
D-90
MOTOROLA
15
0
0
RESET:
The FRZ bits specify the TPU microengine response to the IMB FREEZE signal. Refer
to Table D-57.
CCL controls the latching of channel conditions (MRL and TDL) when the CHAN reg-
ister is written.
These bits are TPU2 breakpoint enables. Setting a bit enables a breakpoint condition.
Table D-58 shows the different breakpoint enable bits.
If an internal breakpoint caused the TPU2 to enter the halted state, the TPU2 asserts
the BKPT signal on the IMB and sets the BKPT flag. BKPT remains set until the TPU2
recognizes a breakpoint acknowledge cycle, or until the IMB FREEZE signal is
asserted.
0 = Only the pin state condition of the new channel is latched as a result of the write
1 = Pin state, MRL, and TDL conditions of the new channel are latched as a result
14
0
0
Enable Bit
CHAN register microinstruction.
of a write CHAN register microinstruction.
BM
BC
BH
BP
BL
BT
13
0
0
12
Break if PC equals PC breakpoint register
Break if CHAN register equals channel breakpoint register at beginning of state or
when CHAN is changed through microcode
Break if host service latch is asserted at beginning of state
Break if link service latch is asserted at beginning of state
Break if MRL is asserted at beginning of state
Break if TDL is asserted at beginning of state
0
0
11
0
0
Table D-58 Breakpoint Enable Bits
FRZ[1:0]
00
01
10
11
10
0
0
Table D-57 FRZ[1:0] Encoding
9
0
0
8
0
0
Freeze at end of current microcycle
Freeze at next time-slot boundary
BKPT
7
0
Function
TPU2 Response
Ignore freeze
PCBK
Reserved
6
0
CHBK
5
0
SRBK
4
0
TPUF
3
0
MC68HC16Y3/916Y3
USER’S MANUAL
2
0
0
$YFFE06
1
0
0
0
0
0