MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 250

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

11-18
MOTOROLA
Data transfer is synchronized with the internally-generated serial clock SCK. Control
bits, CPHA and CPOL, in SPCR0, control clock phase and polarity. Combinations of
CPHA and CPOL determine upon which SCK edge to drive outgoing data from the
MOSI pin and to latch incoming data from the MISO pin.
Baud rate is selected by writing a value from 2 to 255 into SPBR[7:0] in SPCR0. The
QSPI uses a modulus counter to derive the SCK baud rate from the MCU system
clock.
The following expressions apply to the SCK baud rate:
Giving SPBR[7:0] a value of zero or one disables the baud rate generator and SCK
assumes its inactive state.
The DSCK bit in each command RAM byte inserts either a standard (DSCK = 0) or
user-specified (DSCK = 1) delay from chip-select assertion until the leading edge of
the serial clock. The DSCKL field in SPCR1 determines the length of the user-defined
delay before the assertion of SCK. The following expression determines the actual de-
lay before SCK:
where DSCKL[6:0] equals {1,2,3,..., 127}.
When DSCK equals zero, DSCKL[6:0] is not used. Instead, the PCS valid-to-SCK
transition is one-half the SCK period.
There are two transfer length options. The user can choose a default value of eight
bits, or a programmed value from 8 to 16 bits, inclusive. The programmed value must
be written into BITS[3:0] in SPCR0. The BITSE bit in each command RAM byte deter-
mines whether the default value (BITSE = 0) or the BITS[3:0] value (BITSE = 1) is
used. Table 11-3 shows BITS[3:0] encoding.
SPBR[7:0]
PCS to SCK Delay
SCK Baud Rate
QUEUED SERIAL MODULE
=
------------------------------------------------------------------------- -
2 SCK Baud Rate Desired
or
=
------------------------------------ -
2 SPBR[7:0]
=
DSCKL[6:0]
------------------------------ -
f
sys
f
sys
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sys
MC68HC16Y3/916Y3
USER’S MANUAL