MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 433

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

BITS[3:0] — Bits Per Transfer
CPOL — Clock Polarity
CPHA — Clock Phase
SPBR[7:0] — Serial Clock Baud Rate
MC68HC16Y3/916Y3
USER’S MANUAL
In master mode, when BITSE is set in a command RAM byte, BITS[3:0] determines
the number of data bits transferred. When BITSE is cleared, eight bits are transferred.
Reserved values default to eight bits. In slave mode, the command RAM is not used
and the setting of BITSE has no effect on QSPI transfers. Instead, the BITS[3:0] field
determines the number of bits the QSPI will receive during each transfer before storing
the received data.
Table D-38 shows the number of bits per transfer.
CPOL is used to determine the inactive state of the serial clock (SCK). It is used with
CPHA to produce a desired clock/data relationship between master and slave devices.
CPHA determines which edge of SCK causes data to change and which edge causes
data to be captured. CPHA is used with CPOL to produce a desired clock/data rela-
tionship between master and slave devices.
The QSPI uses a modulus counter to derive the SCK baud rate from the MCU system
clock. Baud rate is selected by writing a value from 2 to 255 into SPBR[7:0]. The
following equation determines the SCK baud rate:
0 = The inactive state of SCK is logic zero.
1 = The inactive state of SCK is logic one.
0 = Data is captured on the leading edge of SCK and changed on the trailing edge
1 = Data is changed on the leading edge of SCK and captured on the trailing edge
of SCK.
of SCK
BITS[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Table D-38 Bits Per Transfer
Bits per Transfer
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
16
10
11
12
13
14
15
8
9
MOTOROLA
D-55