MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 143

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

5.6.5 Bus Exception Control Cycles
MC68HC16Y3/916Y3
USER’S MANUAL
An external device or a chip-select circuit must assert at least one of the DSACK[1:0]
signals or the AVEC signal to terminate a bus cycle normally. Bus exception control
cycles are used when bus cycles are not terminated in the expected manner. There
are two sources of bus exception control cycles.
To control termination of a bus cycle for a bus error condition properly, DSACK, BERR,
and HALT must be asserted and negated synchronously with the rising edge of
CLKOUT. This ensures that setup time and hold time requirements are met for the
same falling edge of the MCU clock when two signals are asserted simultaneously.
Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for more information. Ex-
ternal circuitry that provides these signals must be designed with these constraints in
mind, or the internal bus monitor must be used.
Table 5-13 is a summary of the acceptable bus cycle terminations for asynchronous
cycles in relation to DSACK assertion.
• Bus error signal (BERR)
• Halt signal (HALT)
— When DSACK is not asserted within a specified period after assertion of AS,
— The spurious interrupt monitor asserts internal BERR when an interrupt re-
— External devices can assert BERR to indicate an external bus error.
— HALT can be asserted by an external device to cause single bus cycle opera-
the internal bus monitor asserts internal BERR.
quest is acknowledged and no IARB contention occurs. BERR assertion termi-
nates a cycle and causes the MCU to process a bus error exception.
tion. HALT is typically used for debugging purposes.
BERR during the LPSTOP broadcast cycle is ignored.
15
0
14
0
Figure 5-15 LPSTOP Interrupt Mask Level
13
0
12
0
11
0
10
0
9
0
8
0
7
0
NOTE
6
0
5
0
4
0
3
0
2
IP MASK
1
LPSTOP MASK LEVEL
0
MOTOROLA
5-35