C8051F352 Silicon Laboratories Inc, C8051F352 Datasheet - Page 10

• Manufacturer Part Number: C8051F352
• Description: IC 8051 MCU 8K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F35xr

Specifications of C8051F352

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x16b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: C8051F35x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit
• On-chip Dac: 8 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

C8051F350/1/2/3
19. SMBus .................................................................................................................. 147
20. UART0 ................................................................................................................... 167
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Figure 18.3. Crossbar Priority Decoder with No Pins Skipped ............................... 135
Figure 18.4. Crossbar Priority Decoder with Crystal Pins Skipped ........................ 136
Figure 18.5. XBR0: Port I/O Crossbar Register 0................................................... 138
Figure 18.6. XBR1: Port I/O Crossbar Register 1................................................... 139
Figure 18.7. P0: Port0 Register .............................................................................. 141
Figure 18.8. P0MDIN: Port0 Input Mode Register.................................................. 141
Figure 18.9. P0MDOUT: Port0 Output Mode Register ........................................... 142
Figure 18.10. P0SKIP: Port0 Skip Register............................................................ 142
Figure 18.11. P1: Port1 Register ............................................................................ 143
Figure 18.12. P1MDIN: Port1 Input Mode Register................................................ 143
Figure 18.13. P1MDOUT: Port1 Output Mode Register ......................................... 144
Figure 18.14. P1SKIP: Port1 Skip Register............................................................ 144
Figure 18.15. P2: Port2 Register ............................................................................ 145
Figure 18.16. P2MDOUT: Port2 Output Mode Register ......................................... 145
Table 18.1. Port I/O DC Electrical Characteristics.................................................. 146
Figure 19.1. SMBus Block Diagram ....................................................................... 147
Figure 19.2. Typical SMBus Configuration ............................................................. 148
Figure 19.3. SMBus Transaction ............................................................................ 149
Table 19.1. SMBus Clock Source Selection........................................................... 152
Figure 19.4. Typical SMBus SCL Generation......................................................... 153
Table 19.2. Minimum SDA Setup and Hold Times ................................................. 153
Figure 19.5. SMB0CF: SMBus Clock/Configuration Register ................................ 154
Figure 19.6. SMB0CN: SMBus Control Register.................................................... 156
Table 19.3. Sources for Hardware Changes to SMB0CN ...................................... 157
Figure 19.7. SMB0DAT: SMBus Data Register...................................................... 158
Figure 19.8. Typical Master Transmitter Sequence................................................ 159
Figure 19.9. Typical Master Receiver Sequence.................................................... 160
Figure 19.10. Typical Slave Receiver Sequence.................................................... 161
Figure 19.11. Typical Slave Transmitter Sequence................................................ 162
Table 19.4. SMBus Status Decoding...................................................................... 163
Figure 20.1. UART0 Block Diagram ....................................................................... 167
Figure 20.2. UART0 Baud Rate Logic .................................................................... 168
Figure 20.3. UART Interconnect Diagram .............................................................. 169
Figure 20.4. 8-Bit UART Timing Diagram............................................................... 169
Figure 20.5. 9-Bit UART Timing Diagram............................................................... 170
Figure 20.6. UART Multi-Processor Mode Interconnect Diagram .......................... 171
Figure 20.7. SCON0: Serial Port 0 Control Register .............................................. 172
Figure 20.8. SBUF0: Serial (UART0) Port Data Buffer Register ............................ 173
Table 20.1. Timer Settings for Standard Baud Rates Using the Internal Oscillator 174
Table 20.2. Timer Settings for Standard Baud Rates Using an External Oscillator 174
Table 20.3. Timer Settings for Standard Baud Rates Using an External Oscillator 175
Table 20.4. Timer Settings for Standard Baud Rates Using an External Oscillator 175
Table 20.5. Timer Settings for Standard Baud Rates Using an External Oscillator 176
Rev. 0.4