C8051F352 Silicon Laboratories Inc, C8051F352 Datasheet - Page 95

• Manufacturer Part Number: C8051F352
• Description: IC 8051 MCU 8K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F35xr

Specifications of C8051F352

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x16b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: C8051F35x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit
• On-chip Dac: 8 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

11.6. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the CIP-51's resources and peripherals. The
CIP-51 duplicates the SFRs found in a typical 8051 implementation as well as implementing additional
SFRs used to configure and access the sub-systems unique to the MCU. This allows the addition of new
functionality while retaining compatibility with the MCS-51™ instruction set. Table 11.1 lists the SFRs
implemented in the CIP-51 System Controller.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, IE, etc.) are bit-addressable
as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied addresses in the SFR
space are reserved for future use. Accessing these areas will have an indeterminate effect and should be
avoided. Refer to the corresponding pages of the datasheet, as indicated in Table 11.2, for a detailed
description of each register.
D8
D0
C8 TMR2CN
C0 SMB0CN
F8
F0
E8 ADC0STA PCA0CPL0 PCA0CPH0 PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2 RSTSRC
E0
B8
B0
A8
A0
98
90
88
80
addressable)
PCA0CN
SPI0CN
SCON0
TCON
PSW
ACC
0(8)
(bit
P2
P1
P0
IP
IE
B
Table 11.1. Special Function Register (SFR) Memory Map
OSCXCN
SPI0CFG
PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2
TMR3CN
REF0CN
SMB0CF
P0MDIN
CLKSEL
IDA0CN
SBUF0
PCA0L
TMOD
XBR0
1(9)
SP
ADC0DECL
ADC0COL ADC0COM ADC0COH ADC0BUF
SMB0DAT
TMR3RLL TMR3RLH
TMR2RLL TMR2RLH
SPI0CKR
OSCICN
P1MDIN
EMI0CN
PCA0H
XBR1
DPL
2(A)
TL0
ADC0CGL ADC0CGM ADC0CGH
ADC0DEC
ADC0MD
SPI0DAT
ADC0CF
PFE0CN
OSCICL
ADC0L
DPH
3(B)
TL1
H
Rev. 0.4
P0MDOUT P1MDOUT P2MDOUT
ADC0CN
CPT0CN
ADC0FL
ADC0M
IT01CF
P0SKIP
TMR2L
TMR3L
TH0
4(C)
ADC0FM
CPT0MD
TMR2H
TMR3H
ADC0H
P1SKIP
C8051F350/1/2/3
IDA1
TH1
5(D)
ADC0MUX
ADC0FH
CKMUL
CKCON
FLSCL
IDA0
EIP1
EIE1
6(E)
ADC0DAC
ADC0CLK
VDM0CN
CPT0MX
IDA1CN
PSCTL
FLKEY
PCON
7(F)
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