C8051F352 Silicon Laboratories Inc, C8051F352 Datasheet - Page 43

IC 8051 MCU 8K FLASH 32LQFP

C8051F352

Manufacturer Part Number
C8051F352
Description
IC 8051 MCU 8K FLASH 32LQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F35xr
Datasheets

Specifications of C8051F352

Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x16b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Processor Series
C8051F35x
Core
8051
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
17
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
16 bit
On-chip Dac
8 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No

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ADC0CGH, ADC0CGM, and ADC0CGL registers. The mapping of the gain register is shown in
Figure 5.4.
The offset calibration value adjusts the zero point of the ADC’s transfer function. It is stored as a two’s
complement, 24-bit number. An offset calibration which results in a full-scale positive (0x7FFFFF) or full-
scale negative (0x800000) result will cause an ADC error condition.
The Offset Calibration results are stored in registers ADC0COH, ADC0COM, and ADC0COL. The weight-
ing of the bits in the offset register (in LSBs) are shown below:
The gain calibration value adjusts the slope of the ADC’s transfer function. The gain calibration regsiter
can range from 0 to 2 - 2
error condition.
The Gain Calibration results are stored in registers ADC0CGH, ADC0CGM, and ADC0CGL, as follows:
Example Decoding for Gain Register setting of 0x940000 (10010100 00000000 00000000b):
Slope Adjustment = 2
MSB 22
MSB 22
MSB 22
-2
-2
2
15
23
0
2
2
2
14
22
-1
2
2
2
21
21
21
13
21
-2
ADC0COH
ADC0COH
ADC0CGH
2
2
2
20
20
20
12
20
-3
2
2
2
19
19
19
Figure 5.3. ADC0 Offset Calibration Register Coding
19
11
-4
Figure 5.4. ADC0 Gain Calibration Register Coding
0
2
2
2
18
+ 2
18
18
18
10
-5
-23
-3
. A gain calibration which results in either of these extremes will cause an ADC
2
2
17
17
17
2
17
-6
+ 2
9
2
2
-5
16
16
16
2
16
-7
8
= 1.0 + 0.125 + 0.03125 = 1.15625
2
2
15
15
15
2
15
-8
7
24-bit ADC (C8051F350/1)
16-bit ADC (C8051F352/3)
2
2
14
14
14
2
14
-9
6
2
2
13
13
13
2
-10
13
5
ADC0COM
ADC0COM
ADC0CGM
Rev. 0.4
2
2
12
12
12
2
-11
12
4
2
2
11
11
11
2
-12
11
3
2
2
10
10
10
2
-13
10
2
2
2
2
9
9
9
-14
9
1
2
2
2
8
8
-15
8
8
0
C8051F350/1/2/3
2
2
2
7
7
-16
7
7
-1
2
2
2
6
6
-17
6
6
-2
2
2
2
5
-18
5
5
5
-3
ADC0COL
ADC0CGL
ADC0COL
2
2
2
4
4
-19
4
4
-4
2
2
2
3
3
-20
3
3
-5
2
2
2
2
2
-21
2
2
-6
2
2
2
1
1
-22
1
1
-7
LSB
LSB
LSB
2
2
2
-23
0
-8
43

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