C8051F352 Silicon Laboratories Inc, C8051F352 Datasheet - Page 112

IC 8051 MCU 8K FLASH 32LQFP

C8051F352

Manufacturer Part Number
C8051F352
Description
IC 8051 MCU 8K FLASH 32LQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F35xr
Datasheets

Specifications of C8051F352

Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x16b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Processor Series
C8051F35x
Core
8051
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
17
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
16 bit
On-chip Dac
8 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No

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C8051F350/1/2/3
14.1. Power-On Reset
During power-up, the device is held in a reset state and the /RST pin is driven low until V
V
increases (V
power-on and V
cause the device to be released from reset before V
1 ms, the power-on reset delay (T
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000) software can
read the PORSF flag to determine if a power-up was the cause of reset. The contents of internal data
memory should be assumed to be undefined after a power-on reset. The V
a power-on reset.
112
RST
. A delay occurs before the device is released from reset; the delay decreases as the V
DD
ramp time is defined as how fast V
DD
Logic HIGH
Logic LOW
Figure 14.2. Power-On and
monitor reset timing. The maximum V
2.70
2.55
2.0
1.0
/RST
V
PORDelay
RST
Power-On
Reset
) is typically less than 0.3 ms.
T
PORDelay
Rev. 0.4
DD
DD
V
reaches the V
DD
ramps from 0 V to V
DD
Monitor Reset Timing
ramp time is 1 ms; slower ramp times may
Monitor
Reset
VDD
RST
level. For ramp times less than
DD
monitor is enabled following
RST
). Figure 14.2. plots the
VDD
DD
t
settles above
DD
ramp time

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