C8051F352 Silicon Laboratories Inc, C8051F352 Datasheet - Page 41

• Manufacturer Part Number: C8051F352
• Description: IC 8051 MCU 8K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F35xr

Specifications of C8051F352

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x16b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: C8051F35x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit
• On-chip Dac: 8 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

5.1.3. Modulator Clock
The ADC0CLK register (Figure 5.8) holds the Modulator Clock (MDCLK) divisor value. The modulator
clock determines the switching frequency for the ADC sampling capacitors. Optimal performance will be
achieved when the MDCLK frequency is equal to 2.4576 MHz. The modulator samples the input at a rate
of MDCLK / 128.
5.1.4. Decimation Ratio
The decimation ratio of the ADC filters is selected by the DECI[10:0] bits in the ADC0DECH and
ADC0DECL registers (Figure 5.9 and Figure 5.10, respectively). The decimation ratio is equal to 1 +
DECI[10:0]. The decimation ratio determines how many modulator samples are used to generate a single
output word. The ADC output word rate is equal to the modulator sampling rate divided by the decimation
ratio. For more information on how the ADC output word rate is derived, see Figure 5.8 and Figure 5.10.
Higher decimation ratios will produce lower-noise results over a longer conversion period. The minimum
decimation ratio is 20. When using the fast filter output, the decimation ratio must be set to a multi-
ple of 8.
Channel
Channel
AIN+
AIN-
Figure 5.2. ADC0 Buffer Control
Bypass Buffer
Bypass Buffer
High Buffer+
Low Buffer+
High Buffer-
Low Buffer-
Rev. 0.4
AD0BPHE
AD0BNHE
AD0BPLE
AD0BPS1
AD0BPS0
AD0BNLE
AD0BNS1
AD0BNS0
To PGA
To PGA
C8051F350/1/2/3
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