C8051F352 Silicon Laboratories Inc, C8051F352 Datasheet - Page 73

• Manufacturer Part Number: C8051F352
• Description: IC 8051 MCU 8K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F35xr

Specifications of C8051F352

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x16b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: C8051F35x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit
• On-chip Dac: 8 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

9.
C8051F350/1/2/3 devices include an on-chip programmable voltage comparator, Comparator0, shown in
Figure 9.1.
The Comparator offers programmable response time and hysteresis and two outputs that are optionally
available at the Port pins: a synchronous “latched” output (CP0), or an asynchronous “raw” output (CP0A).
The asynchronous CP0A signal is available even when the system clock is not active. This allows the
Comparator to operate and generate an output with the device in STOP mode. When assigned to a Port
pin, the Comparator output may be configured as open drain or push-pull (see
tialization” on page
“14.5. Comparator0 Reset” on page
The Comparator output can be polled in software, used as an interrupt source, and/or routed to a Port pin.
When routed to a Port pin, the Comparator output is available asynchronous or synchronous to the system
clock; the asynchronous output is available even in STOP mode (with no system clock active). When dis-
abled, the Comparator output (if assigned to a Port I/O pin) defaults to the logic low state, and its supply
current falls to less than 100 nA. Comparator inputs can be externally driven from -0.25 V to
(V
Table 9.1.
The Comparator response time may be configured in software via the CPT0MD register (see Figure 9.4).
Selecting a longer response time reduces the Comparator supply current. See Table 9.1 for complete tim-
ing and power consumption specifications.
DD
) + 0.25 V without damage or upset. The complete Comparator electrical specifications are given in
Comparator0
CP0 +
CP0 -
Figure 9.1. Comparator0 Functional Block Diagram
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0
CP0OUT
CP0MD1
CP0MD0
CP0RIF
CP0RIE
CP0FIF
CP0FIE
CP0EN
137). Comparator0 may also be used as a reset source (see
+
-
114).
VDD
GND
CP0RIF
CP0FIF
Decision
Reset
Tree
Rev. 0.4
(SYNCHRONIZER)
D
SET
CLR
Q
Q
0
1
0
1
D
SET
CLR
Q
Q
CP0EN
C8051F350/1/2/3
(asynchronous output)
(synchronous output)
0
1
EA
CP0A
CP0
Section “18.2. Port I/O Ini-
0
1
Interrupt
CP0
Section
73