C8051F352 Silicon Laboratories Inc, C8051F352 Datasheet - Page 49
C8051F352
Manufacturer Part Number
C8051F352
Description
IC 8051 MCU 8K FLASH 32LQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F35xr
Specifications of C8051F352
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x16b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Processor Series
C8051F35x
Core
8051
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
17
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
16 bit
On-chip Dac
8 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F352
Manufacturer:
SILICON
Quantity:
364
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Manufacturer:
Silicon Laboratories Inc
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Silicon Laboratories Inc
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Manufacturer:
SILICON LABS/芯科
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20 000
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Manufacturer:
Silicon Laboratories Inc
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C8051F352R
Manufacturer:
Silicon Laboratories Inc
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10 000
Bits 7-0: ADC0CLK: ADC0 Modulator Clock Divisor.
Note: The Modulator Sampling Rate is not the ADC Output Word Rate. See Section 5.1.4 for
Bits 7-3: Unused: Read = 00000b, Write = don’t care.
Bits 2-0: DECI[10:8]: ADC0 Decimation Ratio Register, Bits 10-8.
This SFR can only be modified when ADC0 is in IDLE mode.
R/W
R/W
Bit7
Bit7
-
Figure 5.9. ADC0DECH: ADC0 Decimation Ratio Register High Byte
This register establishes the Modulator Clock (MDCLK), by dividing down the system clock
(SYSCLK). The input signal is sampled by the modulator at a frequency of MDCLK / 128.
For optimal performance, the divider should be chosen such that the modulator clock is
equal to 2.4576 MHz (modulator sampling rate = 19.2 kHz).
The system clock is divided according to the equation:
MDCLK = SYSCLK / (ADC0CLK + 1)
details.
This register contains the high bits of the 11-bit ADC Decimation Ratio. The decimation ratio
determines the output word rate of ADC0, based on the Modulator Clock (MDCLK). See the
ADC0DECL register description for more information.
R/W
R/W
Bit6
Bit6
-
Figure 5.8. ADC0CLK: ADC0 Modulator Clock Divisor
R/W
R/W
Bit5
Bit5
-
R/W
R/W
Bit4
Bit4
-
ADC0CLK
Rev. 0.4
R/W
R/W
Bit3
Bit3
-
DECI10
R/W
R/W
Bit2
Bit2
C8051F350/1/2/3
DECI9
R/W
R/W
Bit1
Bit1
SFR Address:
SFR Address:
DECI8
R/W
R/W
Bit0
Bit0
0xF7
0x9B
00000000
Reset Value
Reset Value
00000111
49