C8051F352 Silicon Laboratories Inc, C8051F352 Datasheet - Page 147

• Manufacturer Part Number: C8051F352
• Description: IC 8051 MCU 8K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F35xr

Specifications of C8051F352

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x16b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: C8051F35x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit
• On-chip Dac: 8 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

19.
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System
Management Bus Specification, version 1.1, and compatible with the I2C serial bus. Reads and writes to
the interface by the system controller are byte oriented with the SMBus interface autonomously controlling
the serial transfer of the data. Data can be transferred at up to 1/10th of the system clock as a master or
slave (this can be faster than allowed by the SMBus specification, depending on the system clock used). A
method of extending the clock-low duration is available to accommodate devices with different speed
capabilities on the same bus.
The SMBus interface may operate as a master and/or slave, and may function on a bus with multiple mas-
ters. The SMBus provides control of SDA (serial data), SCL (serial clock) generation and synchronization,
arbitration logic, and START/STOP control and generation. Three SFRs are associated with the SMBus:
SMB0CF configures the SMBus; SMB0CN controls the status of the SMBus; and SMB0DAT is the data
register, used for both transmitting and receiving SMBus data and slave addresses.
M
R
A
S
T
E
Interrupt
Request
SMBus
M
X
O
D
E
T
SMB0CN
S
T
A
O
S
T
A
C
K
R
Q
O
A
R
B
L
S
T
A
C
K
S
I
Arbitration
SCL Synchronization
SCL Generation (Master Mode)
SDA Control
IRQ Generation
SMBUS CONTROL LOGIC
M
E
N
S
B
N
H
I
Figure 19.1. SMBus Block Diagram
U
SMB0CF
B
S
Y
E
X
T
H
O
D
L
M
O
S
B
T
E
7
M
S
B
F
T
E
6
SMB0DAT
M
S
B
C
S
1
5
M
S
B
C
S
0
4
Data Path
3
Control
2
1
0
Rev. 0.4
00
01
10
11
Control
Control
SDA
SCL
T0 Overflow
T1 Overflow
TMR2H Overflow
TMR2L Overflow
FILTER
FILTER
N
N
C8051F350/1/2/3
SDA
SCL
C
R
O
R
S
S
B
A
Port I/O
147