C8051F352 Silicon Laboratories Inc, C8051F352 Datasheet - Page 11

• Manufacturer Part Number: C8051F352
• Description: IC 8051 MCU 8K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F35xr

Specifications of C8051F352

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x16b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: C8051F35x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit
• On-chip Dac: 8 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

21. Serial Peripheral Interface (SPI0) ....................................................................... 177
22. Timers ................................................................................................................... 191
23. Programmable Counter Array ............................................................................ 207
Table 20.6. Timer Settings for Standard Baud Rates Using an External Oscillator 176
Figure 21.1. SPI Block Diagram ............................................................................. 177
Figure 21.2. Multiple-Master Mode Connection Diagram ....................................... 180
Figure 21.3. 3-Wire Single Master and Single Slave Mode Connection Diagram .. 180
Figure 21.4. 4-Wire Single Master and Slave Mode Connection Diagram ............. 180
Figure 21.5. Data/Clock Timing Relationship ......................................................... 182
Figure 21.6. SPI0CFG: SPI0 Configuration Register ............................................. 183
Figure 21.7. SPI0CN: SPI0 Control Register.......................................................... 184
Figure 21.8. SPI0CKR: SPI0 Clock Rate Register ................................................. 185
Figure 21.9. SPI0DAT: SPI0 Data Register............................................................ 186
Figure 21.10. SPI Master Timing (CKPHA = 0)...................................................... 187
Figure 21.11. SPI Master Timing (CKPHA = 1)...................................................... 187
Figure 21.12. SPI Slave Timing (CKPHA = 0)........................................................ 188
Figure 21.13. SPI Slave Timing (CKPHA = 1)........................................................ 188
Table 21.1. SPI Slave Timing Parameters ............................................................. 189
Figure 22.1. T0 Mode 0 Block Diagram.................................................................. 192
Figure 22.2. T0 Mode 2 Block Diagram.................................................................. 193
Figure 22.3. T0 Mode 3 Block Diagram.................................................................. 194
Figure 22.4. TCON: Timer Control Register ........................................................... 195
Figure 22.5. TMOD: Timer Mode Register ............................................................. 196
Figure 22.6. CKCON: Clock Control Register ........................................................ 197
Figure 22.7. TL0: Timer 0 Low Byte ....................................................................... 198
Figure 22.8. TL1: Timer 1 Low Byte ....................................................................... 198
Figure 22.9. TH0: Timer 0 High Byte...................................................................... 198
Figure 22.10. TH1: Timer 1 High Byte.................................................................... 198
Figure 22.11. Timer 2 16-Bit Mode Block Diagram ................................................ 199
Figure 22.12. Timer 2 8-Bit Mode Block Diagram .................................................. 200
Figure 22.13. TMR2CN: Timer 2 Control Register ................................................. 201
Figure 22.14. TMR2RLL: Timer 2 Reload Register Low Byte ................................ 202
Figure 22.15. TMR2RLH: Timer 2 Reload Register High Byte............................... 202
Figure 22.16. TMR2L: Timer 2 Low Byte................................................................ 202
Figure 22.17. TMR2H Timer 2 High Byte ............................................................... 202
Figure 22.18. Timer 3 16-Bit Mode Block Diagram ................................................ 203
Figure 22.19. Timer 3 8-Bit Mode Block Diagram .................................................. 204
Figure 22.20. TMR3CN: Timer 3 Control Register ................................................. 205
Figure 22.21. TMR3RLL: Timer 3 Reload Register Low Byte ................................ 206
Figure 22.22. TMR3RLH: Timer 3 Reload Register High Byte............................... 206
Figure 22.23. TMR3L: Timer 3 Low Byte................................................................ 206
Figure 22.24. TMR3H Timer 3 High Byte ............................................................... 206
Figure 23.1. PCA Block Diagram............................................................................ 207
Figure 23.2. PCA Counter/Timer Block Diagram.................................................... 208
Table 23.1. PCA Timebase Input Options .............................................................. 208
Rev. 0.4
C8051F350/1/2/3
11