C8051F352 Silicon Laboratories Inc, C8051F352 Datasheet - Page 77

• Manufacturer Part Number: C8051F352
• Description: IC 8051 MCU 8K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F35xr

Specifications of C8051F352

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x16b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: C8051F35x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit
• On-chip Dac: 8 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

9.1.
Figure 9.5 shows the external pin connections for the comparator. The positive and negative inputs to the
comparator can each be routed to one of eight different pins using the comparator mux. Comparator out-
puts can optionally be routed to port pins using the Crossbar circuitry.
The comparator inputs (CP0+ and CP0-) are selected in the CPT0MX register (Figure 9.6). The CMX0P1-
CMX0P0 bits select the comparator’s positive input; the CMX0N1-CMX0N0 bits select the comparator’s
negative input. Important Note About Comparator Inputs: The Port pins selected as comparator inputs
should be configured as analog inputs in their associated Port configuration register, and configured to be
skipped by the Crossbar.
Two versions of the comparator output can be routed to port pins, using the Port I/O Crossbar. The raw
(asynchronous) comparator output CP0A is enabled using bit 5 in the XBR0 register, and will be available
at P1.2. The CP0 output (synchronized to SYSCLK) is available at P1.3 when it is enabled with bit 4 in the
XBR0 register.
Comparator0 Inputs and Outputs
P0.0
P0.2
P0.4
P0.6
P1.0
P1.2
P1.4
P1.6
P0.1
P0.3
P0.5
P0.7
P1.1
P1.3
P1.5
P1.7
Figure 9.5. Comparator Pin Connections
CP0 +
CP0 -
CPT0MX
Rev. 0.4
+
-
GND
VDD
(SYNCHRONIZER)
D
SET
CLR
Q
Q
D
SET
CLR
Q
Q
C8051F350/1/2/3
XBR0
0
1
0
1
CP0A
CP0
P1.5
P1.4
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