HD6417020SVX12I Renesas Electronics America, HD6417020SVX12I Datasheet - Page 108

• Manufacturer Part Number: HD6417020SVX12I
• Description: IC SUPERH MPU ROMLESS 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SVX12I

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 12.5MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

6.5.3
If a break is attempted at the task A return destination instruction fetch, task B is activated before
the UBC interrupt by interrupt B generated during task A processing, and the UBC interrupt is
handled after the interrupt B exception handling.
(1) Cause
The SH7032/SH7034 chip operates as follows.
It actually takes at least two cycles for the UBC interrupt generated by the address 0x00011a0c
instruction fetch cycle to be sent to the interrupt controller and interrupt exception handling to
begin. However, as shown in figure 6.3, when the UBC interrupt is generated, previously
generated interrupt B initiated by task B is accepted first, and the UBC interrupt is accepted after
completion of the interrupt B exception handling.
(2) Remedy
There is no way of preventing this operation by hardware. A software solution, such as the use of
a flag, must be employed.
Break
condition
Instruction Fetch Break
0x02000030
0x00011a0a
0x00011a0c
<Address>
(0xf000978 Overrun fetch)
0xf000974
Interrupt B accepted
Instruction replaced by interrupt
exception handling
Task B first instruction fetch
UBC first instruction fetch
Overrun fetch
<Description>
(instruction replaced by interrupt
exception handling)
F D
Figure 6.3
F
E E
Interrupt exception
handling
M M E
UBC Operation
UBC interrupt accepted
M E E
F
D E E
f
Interrupt exception
M M
handling
E
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M
E E
F