HD6417020SVX12I Renesas Electronics America, HD6417020SVX12I Datasheet - Page 74

• Manufacturer Part Number: HD6417020SVX12I
• Description: IC SUPERH MPU ROMLESS 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SVX12I

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 12.5MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

3. Clears the vector base register (VBR) to H'00000000, and sets interrupt mask bits I3–I0 in the
4. Loads the values read from the exception vector table into PC and SP and starts program
Further, make sure to carry out a power-on reset when turning on the power of the system.
4.2.3
When the NMI pin is high, a low input at the RES pin drives the chip into the manual reset state.
To be assured of resetting the LSI, drive the RES pin low for at least 20 t
initializes the internal state of the CPU and all registers of the on-chip peripheral modules except
the bus state controller, pin function controller and I/O ports. Since a manual reset does not affect
the bus state controller, the DRAM refresh control function operates even if the manual reset state
continues for a long time. When a manual reset is performed during the bus cycle, the manual
reset exception processing waits for the end of the bus cycle before beginning. The manual reset
thus cannot be used to abort the bus cycle. For the pin states during the manual reset state, see
appendix B, Pin States.
While the NMI pin remains low, if the RES pin is held low for a certain time then driven high in
the manual reset state, manual reset exception processing begins. The CPU carries out the same
operations as for a power-on reset.
4.3
4.3.1
Address errors occur during instruction fetches and data reading/writing as shown in table 4.5.
52 RENESAS
status register (SR) to H'F (1111).
execution.
Manual Reset
Address Errors
Address Error Sources
cyc
. A manual reset