HD6417020SVX12I Renesas Electronics America, HD6417020SVX12I Datasheet - Page 193

• Manufacturer Part Number: HD6417020SVX12I
• Description: IC SUPERH MPU ROMLESS 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SVX12I

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 12.5MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

9.2
9.2.1
DMA source address registers 0–3 (SAR0–SAR3) are 32-bit read/write registers that specify the
source address of a DMA transfer. During a DMA transfer, these registers indicate the next source
address (in single-address mode, SAR is ignored in transfers from external devices with DACK to
memory-mapped external devices or external memory).
The initial value after resets or in standby mode is undefined.
9.2.2
DMA destination address registers 0–3 (DAR0–DAR3) are 32-bit read/write registers that specify
the destination address of a DMA transfer. During a DMA transfer, these registers indicate the
next destination address (in single-address mode, DAR is ignored in transfers from memory-
mapped external devices or external memory to external devices with DACK). The initial value
after resets or in standby mode is undefined.
174 RENESAS
Initial value:
Initial value:
Initial value:
Initial value:
Bit name:
Bit name:
Bit name:
Bit name:
Register Descriptions
DMA Source Address Registers 0–3 (SAR0–SAR3)
DMA Destination Address Registers 0–3 (DAR0–DAR3)
R/W:
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
Bit:
R/W
R/W
R/W
R/W
31
—
23
—
31
—
23
—
R/W
R/W
R/W
R/W
30
—
22
—
30
—
22
—
R/W
R/W
R/W
R/W
29
—
21
—
29
—
21
—
R/W
R/W
R/W
R/W
28
—
20
—
28
—
20
—
R/W
R/W
27
—
27
—
R/W
R/W
26
—
…
…
…
…
26
—
…
…
…
…
R/W
R/W
25
—
25
—
R/W
R/W
R/W
R/W
24
—
—
24
—
—
0
0