HD6417020SVX12I Renesas Electronics America, HD6417020SVX12I Datasheet - Page 178

• Manufacturer Part Number: HD6417020SVX12I
• Description: IC SUPERH MPU ROMLESS 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SVX12I

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 12.5MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

8.10.1
This LSI has the bus arbitration function which can give bus ownership to an external device when
the device requests the bus ownership. When BREQ is input and the bus cycle being executed by
the CPU or DMAC is completed, BACK becomes low and a bus is released for an external device.
At this time, the following operates when bus arbitration conflicts with refresh.
1. If DRAM refresh is requested in this LSI when a bus is released and BACK is low, BACK
2. When BREQ changes from high to low and internal refresh is requested at the timing of the
158 RENESAS
becomes high and the occurrence of the refresh request can be informed externally. At this
time, the external device may generate a bus cycle when BREQ is low even if BACK is high.
Therefore, a bus remains released to the external device. Then, when BREQ becomes high, this
LSI gets bus ownership, and executes refresh and the bus cycle of the CPU or DMAC. After
the external device gets bus ownership and BACK is low, refresh is requested when BACK
becomes high even if the low level of BREQ is input. Therefore, turn BREQ high immediately
to release a bus for this LSI to hold DRAM data (See figure 8.36).
bus release of this LSI, BACK may remain high (do not become low). A bus is released to the
external device since the low level of BREQ is input. This operation is based on the above
specification (1). To hold DRAM data, turn BREQ high and release a bus to this LSI
immediately when the external device detects that BACK does not change to low during a
fixed time this LSI (See figure 8.37). When a refresh request is generated and BACK returns
to high, as shown in figure 8.37, a momentary narrow pulse-shaped spike may be output where
BACK was originally supposed to become low.
The Operation of Bus Arbitration
Address, data, strobe pin:
Bus release response
High-level output
BREQ received
High impedance
Bus released
Strobe pin:
SuperH
Figure 8.35 Bus Release Procedure
BACK = low
BREQ = low
BACK
Bus acquisition
External device
Bus request
acknowledge