HD6417020SVX12I Renesas Electronics America, HD6417020SVX12I Datasheet - Page 451
HD6417020SVX12I
Manufacturer Part Number
HD6417020SVX12I
Description
IC SUPERH MPU ROMLESS 100TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7020r
Datasheet
1.HD6417020SVX12IV.pdf
(511 pages)
Specifications of HD6417020SVX12I
Core Processor
SH-1
Core Size
32-Bit
Speed
12.5MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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18.4.2
Canceling the Standby Mode
The standby mode is canceled by an NMI interrupt, a power-on reset, or a manual reset.
Cancellation by an NMI: When a rising edge or falling edge (as selected by the NMIE bit in
interrupt control register ICR of interrupt controller INTC) is detected at the NMI pin, the clock
oscillator begins operating. At first, clock pulses are supplied only to the watchdog timer. After the
time that was selected before entering the standby mode using clock select bits 2–0 (CKS2–CKS0)
in the timer control/status register TCSR of the watchdog timer WDT, the watchdog timer
overflows. After the overflow, the clock is considered stable and supplied to the entire chip. The
standby mode is canceled and the NMI exception-processing sequence begins.
When the standby mode is cleared by an NMI interrupt, bits CKS2–CKS0 must be set so that the
WDT overflow interval is equal to or greater than the clock settling time. When the standby mode
is cleared when the fall edge has been selected in the NMI bit, be sure that the NMI pin is high
when standby is entered (when the clock is halted) and low when the chip returns from standby
(clock starts up after oscillator is stabilized). Likewise, when the standby mode is cleared when the
rise edge has been selected in the NMI bit, be sure that the NMI pin is low when standby is
entered (clock halted) and high when the chip returns from standby (clock starts up after oscillator
is stabilized).
Cancellation by a Power-On Reset: If the RES signal goes low while the NMI signal is high, the
standby mode is canceled and the power-on reset state is entered. If the NMI signal is brought
from low to high in order to set the LSI for power-on resets, the standby mode will not be canceled
by an NMI interrupt, because the NMI signal is initialized for the falling edge in the standby mode
(by the NMIE bit).
Cancellation by a Manual Reset: If the RES signal goes low while the NMI signal is low, the
standby mode is canceled and the manual reset state is entered. If the NMI signal is brought from
high to low in order to set the LSI for manual resets, the standby mode will first be canceled by an
NMI interrupt, because the NMI signal is initialized for the falling edge in the standby mode (by
the NMIE bit).
RENESAS 438
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