HD6417020SVX12I Renesas Electronics America, HD6417020SVX12I Datasheet - Page 361

• Manufacturer Part Number: HD6417020SVX12I
• Description: IC SUPERH MPU ROMLESS 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SVX12I

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 12.5MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

13.2
13.2.1
The receive shift register (RSR) receives serial data. Data input at the RxD pin are loaded into the
RSR in the order received, LSB (bit 0) first. In this way the SCI converts received data to parallel
form. When one byte has been received, it is automatically transferred to the receive data register
(RDR). The CPU cannot read or write the RSR directly.
13.2.2
The receive data register (RDR) stores serial receive data. The SCI completes the reception of one
byte of serial data by moving the received data from the receive shift register (RSR) into the RDR
for storage. The RSR is then ready to receive the next data. This double buffering allows the SCI
to receive data continuously.
The CPU can read but not write the RDR. The RDR is initialized to H'00 by a reset or in standby
mode.
13.2.3
The transmit shift register (TSR) transmits serial data. The SCI loads transmit data from the
transmit data register (TDR) into the TSR, then transmits the data serially from the TxD pin, LSB
(bit 0) first. After transmitting one data byte, the SCI automatically loads the next transmit data
from the TDR into the TSR and starts transmitting again. If the TDRE bit of the SSR is 1,
however, the SCI does not load the TDR contents into the TSR. The CPU cannot read or write the
TSR directly.
RENESAS 344
Initial value:
Bit name:
Bit name:
Bit name:
Register Descriptions
Receive Shift Register
Receive Data Register
Transmit Shift Register
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
—
—
7
7
0
R
7
—
—
6
6
0
R
6
—
—
5
5
0
R
5
—
—
4
4
0
R
4
—
—
3
3
0
R
3
—
—
2
2
0
R
2
—
—
1
1
0
R
1
—
—
0
0
0
R
0