HD6417020SVX12I Renesas Electronics America, HD6417020SVX12I Datasheet - Page 15

• Manufacturer Part Number: HD6417020SVX12I
• Description: IC SUPERH MPU ROMLESS 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SVX12I

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 12.5MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

5.4
5.5
5.5
Section 6 User Break Controller (UBC)
6.1
6.2
6.3
6.4
6.5
Section 7 Clock Pulse Generator (CPG)
7.1
7.2
7.3
Section 8 Bus State Controller (BSC)
8.1
8.2
5.3.2
Interrupt Operation ............................................................................................................ 70
5.4.1
5.4.2
Interrupt Response Time.................................................................................................... 73
Usage Notes ....................................................................................................................... 74
Overview............................................................................................................................ 75
6.1.1
6.1.2
6.1.3
Register Descriptions......................................................................................................... 77
6.2.1
6.2.2
6.2.3
Operation ........................................................................................................................... 81
6.3.1
6.3.2
6.3.3
Setting User Break Conditions .......................................................................................... 84
Notes.................................................................................................................................. 86
6.5.1
6.5.2
6.5.3
Overview............................................................................................................................ 89
Clock Source...................................................................................................................... 89
7.2.1
7.2.2
Usage Notes ....................................................................................................................... 91
Overview............................................................................................................................ 93
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
Register Descriptions......................................................................................................... 97
8.2.1
Interrupt Control Register (ICR) .......................................................................... 69
Interrupt Sequence................................................................................................ 70
Stack after Interrupt Exception Processing .......................................................... 72
Features ................................................................................................................ 75
Block Diagram...................................................................................................... 75
Register Configuration .........................................................................................
Break Address Registers (BAR) .......................................................................... 77
Break Address Mask Register (BAMR)...............................................................
Break Bus Cycle Register (BBR) .........................................................................
Flow of the User Break Operation........................................................................ 81
Break on Instruction Fetch Cycles to On-Chip Memory...................................... 84
Program Counter (PC) Value Saved in User Break Interrupt Exception
Processing.............................................................................................................
On-Chip Memory Instruction Fetch .....................................................................
Instruction Fetch at Branches ...............................................................................
Instruction Fetch Break ........................................................................................ 87
Connecting a Crystal Resonator ...........................................................................
External Clock Input ............................................................................................ 90
Features ................................................................................................................ 93
Block Diagram...................................................................................................... 93
Pin Configuration .................................................................................................
Register Configuration .........................................................................................
Overview of Areas................................................................................................ 96
Bus Control Register (BCR) ................................................................................ 97
...........................................................................
...................................................................... 75
.....................................................................
76
78
79
84
86
86
89
89
93
95
95