HD6417020SVX12I Renesas Electronics America, HD6417020SVX12I Datasheet - Page 125

IC SUPERH MPU ROMLESS 100TQFP

HD6417020SVX12I

Manufacturer Part Number
HD6417020SVX12I
Description
IC SUPERH MPU ROMLESS 100TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7020r
Datasheet

Specifications of HD6417020SVX12I

Core Processor
SH-1
Core Size
32-Bit
Speed
12.5MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

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Bit 15L: CW2
0
1
Bit 14: RASD
0
1
Bit 13: TPC
0
1
Bit 15 (dual-CAS or dual-WE select bit (CW2)): When accessing a 16-bit bus width space,
CW2 selects the dual-CAS or the dual-WE method. When cleared to 0, the CASH, CASL, and
WRL signals are valid ; when set to 1, the CASL, WRH, and WRL signals are valid. When
accessing an 8-bit space, only CASL and WRL signals are valid, regardless of CW2 settings.
Bit 14 (RAS down (RASD)): When DRAM access pauses, RASD determines whether to keep
RAS low while waiting for the next DRAM access (RAS down mode) or return it to high
(RAS up mode). When cleared to 0, the RAS signal returns to high; when set to 1, it stays at
low.
Bit 13 (RAS precharge cycle count (TPC)): TPC selects whether the RAS signal precharge
cycle (T
when 1 is set, a 2-state precharge cycle is inserted.
Initial value:
Initial value:
Bit name:
Bit name:
P
) will be 1 state or 2. When TPC is cleared to 0, a 1-state precharge cycle is inserted;
R/W:
R/W:
Bit:
Bit:
CW2
R/W
15
0
7
0
Description
RAS up mode: Return RAS signal to high and wait for the next DRAM
access (initial value)
RAS down mode: Keep RAS signal low and wait for the next DRAM
access
Description
Inserts 1-state precharge cycle (initial value)
Inserts 2-state precharge cycle
Description
Dual-CAS: CASH, CASL, and WRL signals are valid (initial value)
Dual-WE: CASL, WRH, and WRL signals are valid
RASD
R/W
14
0
6
0
TPC
R/W
13
0
5
0
R/W
BE
12
0
4
0
CDTY
R/W
11
0
3
0
MXE
R/W
10
0
2
0
MXC1
R/W
RENESAS 105
9
0
1
0
MXC0
R/W
8
0
0
0

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