HD6417020SVX12I Renesas Electronics America, HD6417020SVX12I Datasheet - Page 229

• Manufacturer Part Number: HD6417020SVX12I
• Description: IC SUPERH MPU ROMLESS 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SVX12I

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 12.5MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

• Countermeasure
210 RENESAS
Especially as shown in Figure 9.17, if the bus cycle of DMA is a full access to DRAM or if
refresh demand is generated, sampling of DREQ takes place before DACK is output as
mentioned above. This phenomenon is found when one of the following transfers is made with
DREQ set to the level detection in the DMA cycle steal mode, in a system which employs
DRAM (refresh enabled).
To prevent unnecessary DMA transfers, configure the system where DREQ is used for edge
detection and the edge corresponding to the next transfer request occurs after the DACK
output.
DACK
Transfer from a device having DACK to memory in the single address mode (not
restricted to DRAM)
Transfer from DRAM to a device having DACK in the single address mode
Output at DACK write in the dual address mode
Output at DACK read in the dual address mode and DMA transfer using DRAM as a
source
CK
Figure 9.17 Example of DREQ Sampling before Output of DACK
Bus cycle of DRAM
Tp
Sampling point
(Full access)
Tr
Number of states of
Tc
: Bus cycle of DMAC
Figure 9.16 Sampling Points of DREQ
DMAC bus cycle
Refresh
1
2
3
4
Sampling point
When refresh operation is entered
Sampling point of DREQ for DACK output position
differs with presence/absence of the refresh operation.
T1
T2
Sampling point