HD6417020SVX12I Renesas Electronics America, HD6417020SVX12I Datasheet - Page 42

• Manufacturer Part Number: HD6417020SVX12I
• Description: IC SUPERH MPU ROMLESS 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SVX12I

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 12.5MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

2.3
2.3.1
All instructions are RISC type. Their features are as follows:
16-Bit Fixed Length: Every instruction is 16 bits long, making program coding much more
efficient.
One Instruction/Cycle: Basic instructions can be executed in one cycle using the pipeline system.
One-cycle instructions are executed in 50 ns at 20 MHz.
Data Length: Long word is the standard data length for all operations. Memory can be accessed
in bytes, words, or long words. Byte or word data accessed from memory is sign-extended and
handled as long word data. Immediate data is sign-extended for arithmetic operations or zero-
extended for logic operations (handled as long word data).
Table 2.2
CPU of SH7000 Series
MOV.W @(disp,PC),R1
ADD
......................
..
.DATA.W
Note: The address of the immediate data is accessed by @(disp, PC).
Load-Store Architecture: Basic operations are executed between registers. For operations that
involve memory, data is loaded to the registers and executed (load-store architecture). Instructions
such as AND that manipulate bits, however, are executed directly in memory.
Delayed Branch Instructions: Unconditional branch instructions are delayed. Pipeline disruption
during branching is reduced by first executing the instruction that follows the branch instruction,
and then branching. See the SH-1/SH-2 Programming Manual for details.
Table 2.3
CPU of SH7000 Series
BRA
ADD
Multiplication/Accumulation Operation: The five-stage pipeline system and the on-chip
multiplier enable 16-bit
16-bit 16-bit + 42-bit
R1,R0
TRGET
R1, R0
Instruction Features
RISC-Type Instruction Set
Sign Extension of Word Data
Delayed Branch Instructions
H'1234
16-bit
42-bit multiplication/accumulation operations can be executed in 2–3
Description
Data is sign-extended to 32 bits, and
R1 becomes H'00001234. It is next
operated upon by an ADD instruction.
Description
Executes an ADD before
branching to TRGET.
32-bit multiplication operations to be executed in 1–3 cycles.
Conventional CPU
ADD.W R1, R0
BRA
Conventional CPUs
ADD.W #H'1234, R0
TRGET
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