HD6417020SVX12I Renesas Electronics America, HD6417020SVX12I Datasheet - Page 218
HD6417020SVX12I
Manufacturer Part Number
HD6417020SVX12I
Description
IC SUPERH MPU ROMLESS 100TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7020r
Datasheet
1.HD6417020SVX12IV.pdf
(511 pages)
Specifications of HD6417020SVX12I
Core Processor
SH-1
Core Size
32-Bit
Speed
12.5MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
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Manufacturer
Quantity
Price
Part Number:
HD6417020SVX12I
Manufacturer:
HITACHI/日立
Quantity:
20 000
Company:
Part Number:
HD6417020SVX12IV
Manufacturer:
RENESAS
Quantity:
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Company:
Part Number:
HD6417020SVX12IV
Manufacturer:
Renesas Electronics America
Quantity:
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Note: Illustrates the case when DACK is output during the DMAC Read cycle.
Figure 9.13 to 9.22 show the sampling timing of the pin DREQ in the cycle steal mode for
each bus cycle. When no DREQ input is detected at the sampling after the aforementioned
DREQ detection, the next sampling occurs in the next stage in which a DACK signal is output.
If no DREQ input is detected at this time, sampling occurs at every state thereafter.
Figure 9.13 DREQ Sampling Timing in Cycle Steal Mode (Output with DREQ level
Figure 9.14 DREQ Sampling Timing in Cycle Steal Mode (Output with DREQ level
Bus cycle
Bus cycle
DREQ
DREQ
DACK
DACK
detection and DACK active low) (Single address mode, bus cycle = 1 state)
detection and DACK active low) (Dual address mode, bus cycle = 1 state)
CK
CK
CPU
CPU
CPU
CPU
CPU
CPU
DMAC (R) DMAC (W)
DMAC
CPU
DMAC (W): DMAC write cycle
DMAC (R): DMAC read cycle
CPU
CPU
CPU
CPU
RENESAS 199
CPU
CPU
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