HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 1121

IC SUPERH MPU ROMLESS 256BGA

HD6417750SBP200

Manufacturer Part Number
HD6417750SBP200
Description
IC SUPERH MPU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417750SBP200

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 2.07 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417750SBP200
Manufacturer:
HITACHI
0
Part Number:
HD6417750SBP200
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
RD2 *
RD/WR2 *
CKIO2ENB
CA
ASEBRK/BRKACK
Legend:
I:
O: Output
Z: High-impedance (not Pulled Up)
H: High-level output
L:
K: Output state held
PI: Input (Pulled Up)
PZ: High-impedance (Pulled Up)
Notes: 1.
Signal Name
Input (not Pulled Up)
Low-level output
21
2.
3.
4.
5.
6.
7.
8.
9.
10. PZ or O, depending on register setting (FRQCR.CKOEN).
11. Pulled up or not pulled up, depending on register setting (STBCR.PPU).
12. Pulled up or not pulled up, depending on register setting (BCR1.IPUP).
13. Pulled up or not pulled up, depending on register setting (BCR1.OPUP).
14. Pulled up with a built-in pull-up resistance. However it, cannot use for fixation of an
15. Output when refreshing is set (SH7750R only).
16. Z or O, depending on register setting (STBCR2.STHZ) (SH7750R only).
17. Z or O, depending on register setting (TOCR, TCOE)
21
Output when area 2 is used as DRAM.
Output when area 5 is used as PCMCIA.
Output when area 6 is used as PCMCIA.
Z (I) or O on refresh operations, depending on register setting (BCR1.HIZCNT).
Depends on refresh operations.
Z (I) or H (state held), depending on register setting (BCR1.HIZMEM).
Z or O, depending on register setting (STBCR.PHZ).
Output when refreshing is set.
Operation in respective state when CKIO2ENB = 0 (SH7750/SH7750S) (High-level
outputs as SH7750R).
input MD pin at the time of power-on reset. Pull up or down outside this LSI.
O
O
I
I
I/O
I/O
Z *
H *
Z *
H *
PI
I
PI *
Master
20
20
9
9
22
*
*
(Power-On)
20
20
O *
Reset
22
Z *
Z *
PI
I
PI *
Slave
20
20
22
PZ *
PZ *
O *
22
9
9
Master
Z *
O *
Z *
H *
PI
I
PI *
13
13
9
9
22
*
*
O *
20
20
(Manual)
Rev.7.00 Oct. 10, 2008 Page 1035 of 1074
Reset
22
Z *
Z *
PI
I
PI *
Slave
9
9
*
*
22
13
13
O *
22
Z *
Z *
PI
I
PI *
Standby
9
9
*
*
22
13
13
O *
Appendix E Pin Functions
O *
H *
22
4
4
Z *
Z *
PI
I
PI *
Bus
Released
REJ09B0366-0700
9
9
*
*
22
13
13
O *
O *
22
4
Z
Z
Z
I
Z
Hardware
Standby

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