HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 531

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

When software wait insertion is specified by WCR2, the external wait input RDY signal is also
sampled. RDY signal sampling is shown in figure 13.12. A single-cycle wait is specified as a
software wait. Sampling is performed at the transition from the Tw state to the T2 state; therefore,
the RDY signal has no effect if asserted in the T1 cycle or the first Tw cycle. The RDY signal is
sampled on the rising edge of the clock.
Figure 13.12 SRAM Interface Wait State Timing (Wait State Insertion by RDY Signal)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
CKIO
A25–A0
CSn
RD/WR
RD
(read)
D63–D0
(read)
WEn
(write)
D63–D0
(write)
BS
RDY
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
DACKn
(DA)
T1
Tw
Rev.7.00 Oct. 10, 2008 Page 445 of 1074
Twe
Section 13 Bus State Controller (BSC)
T2
REJ09B0366-0700