HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 911

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

19.1
The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt
requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the
user to handle interrupt requests according to user-set priority.
19.1.1
The INTC has the following features.
• Fifteen interrupt priority levels can be set
• NMI noise canceler function
• NMI request masking when SR.BL bit is set to 1
19.1.2
Figure 19.1 shows a block diagram of the INTC.
By setting the three interrupt priority registers, the priorities of on-chip peripheral module
interrupts can be selected from 15 levels for different request sources.
The NMI input level bit indicates the NMI pin state. The pin state can be checked by reading
this bit in the interrupt exception service routine, enabling it to be used as a noise canceler.
It is possible to select whether or not NMI requests are to be masked when the SR.BL bit is set
to 1.
Overview
Features
Block Diagram
Section 19 Interrupt Controller (INTC)
Rev.7.00 Oct. 10, 2008 Page 825 of 1074
Section 19 Interrupt Controller (INTC)
REJ09B0366-0700