HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 50

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

3.4
3.5
3.6
3.7
3.8
Section 4 Caches
4.1
4.2
4.3
Rev.7.00 Oct. 10, 2008 Page xlviii of lxxxiv
REJ09B0366-0700
3.3.6
3.3.7
TLB Functions .................................................................................................................. 86
3.4.1
3.4.2
3.4.3
MMU Functions................................................................................................................ 93
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
MMU Exceptions.............................................................................................................. 96
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
3.6.6
3.6.7
Memory-Mapped TLB Configuration............................................................................... 102
3.7.1
3.7.2
3.7.3
3.7.4
3.7.5
3.7.6
Usage Notes ...................................................................................................................... 109
Overview........................................................................................................................... 111
4.1.1
4.1.2
Register Descriptions ........................................................................................................ 114
Operand Cache (OC)......................................................................................................... 116
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
Single Virtual Memory Mode and Multiple Virtual Memory Mode ................... 85
Address Space Identifier (ASID) ......................................................................... 85
Unified TLB (UTLB) Configuration ................................................................... 86
Instruction TLB (ITLB) Configuration................................................................ 90
Address Translation Method................................................................................ 90
MMU Hardware Management ............................................................................. 93
MMU Software Management .............................................................................. 93
MMU Instruction (LDTLB)................................................................................. 93
Hardware ITLB Miss Handling ........................................................................... 94
Avoiding Synonym Problems .............................................................................. 95
Instruction TLB Multiple Hit Exception.............................................................. 96
Instruction TLB Miss Exception.......................................................................... 96
Instruction TLB Protection Violation Exception ................................................. 98
Data TLB Multiple Hit Exception ....................................................................... 98
Data TLB Miss Exception ................................................................................... 99
Data TLB Protection Violation Exception........................................................... 100
Initial Page Write Exception ................................................................................ 101
ITLB Address Array ............................................................................................ 103
ITLB Data Array 1............................................................................................... 104
ITLB Data Array 2............................................................................................... 105
UTLB Address Array........................................................................................... 106
UTLB Data Array 1 ............................................................................................. 107
UTLB Data Array 2 ............................................................................................. 108
Features................................................................................................................ 111
Register Configuration......................................................................................... 113
Configuration ....................................................................................................... 116
Read Operation .................................................................................................... 120
Write Operation ................................................................................................... 121
Write-Back Buffer ............................................................................................... 122
Write-Through Buffer.......................................................................................... 122
.................................................................................................................. 111