HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 238

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 5 Exceptions
5.4
Table 5.2 shows the types of exceptions, with their relative priorities, vector addresses, and
exception/interrupt codes.
Table 5.2
Exception
Category
Rev.7.00 Oct. 10, 2008 Page 152 of 1074
REJ09B0366-0700
Reset
General
exception
Exception Types and Priorities
Execution
Mode
Abort type
Re-
execution
type
Completion
type
Exceptions
Exception
Power-on reset
Manual reset
H-UDI reset
Instruction TLB multiple-hit
exception
Data TLB multiple-hit exception 1
User break before instruction
execution *
Instruction address error
Instruction TLB miss exception
Instruction TLB protection
violation exception
General illegal instruction
exception
Slot illegal instruction exception 2
General FPU disable exception 2
Slot FPU disable exception
Data address error (read)
Data address error (write)
Data TLB miss exception (read) 2
Data TLB miss exception (write) 2
Data TLB protection
violation exception (read)
Data TLB protection
violation exception (write)
FPU exception
Initial page write exception
Unconditional trap (TRAPA)
User break after instruction
execution *
1
1
Priority
Level
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Priority
Order
2
3
4
0
2
3
4
4
4
4
5
5
6
7
7
8
9
4
10
1
1
1
6
Vector
Address
H'A000 0000 —
H'A000 0000 —
H'A000 0000 —
H'A000 0000 —
H'A000 0000 —
(VBR/DBR)
(VBR)
(VBR)
(VBR)
(VBR)
(VBR)
(VBR)
(VBR)
(VBR)
(VBR)
(VBR)
(VBR)
(VBR)
(VBR)
(VBR)
(VBR)
(VBR)
(VBR/DBR)
Offset
H'100/— H'1E0
H'100
H'400
H'100
H'100
H'100
H'100
H'100
H'100
H'100
H'400
H'400
H'100
H'100
H'100
H'100
H'100
H'100/— H'1E0
Exception
Code
H'000
H'020
H'000
H'140
H'140
H'0E0
H'040
H'0A0
H'180
H'1A0
H'800
H'820
H'0E0
H'100
H'040
H'060
H'0A0
H'0C0
H'120
H'080
H'160