HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 658

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 14 Direct Memory Access Controller (DMAC)
Table 14.5 Selecting On-Chip Peripheral Module Request Mode with RS Bits
RS3 RS2 RS1 RS0
1
Legend:
TMU: Timer unit
SCI:
SCIF: Serial communication interface with FIFO
Notes: 1. SCI/SCIF burst transfer setting is prohibited.
To output a transfer request from an on-chip peripheral module, set the DMA transfer request
enable bit for that module and output a transfer request signal.
For details, see sections 12, Timer Unit (TMU), 15, Serial Communication Interface (SCI), and
16, Serial Communication Interface with FIFO (SCIF).
Rev.7.00 Oct. 10, 2008 Page 572 of 1074
REJ09B0366-0700
0
1
Serial communication interface
2. If input capture interrupt acceptance is set for multiple channels and DE = 1 for each
3. A DMA transfer request by means of an input capture interrupt can be canceled by
*
channel, processing will be executed on the highest-priority channel in response to a
single input capture interrupt.
setting TCR2.ICPE1 = 0 and ICPE0 = 0 in the TMU.
External memory or memory-mapped external device
0
1
0
1
0
1
0
1
0
1
0
DMAC Transfer
Request Source
SCI transmitter
SCI receiver
SCIF transmitter
SCIF receiver
TMU channel 2
TMU channel 2
TMU channel 2
DMAC Transfer
Request Signal
SCTDR1 (SCI
transmit-data-
empty transfer
request)
SCRDR1 (SCI
receive-data-full
transfer request)
SCFTDR2 (SCIF
transmit-data-
empty transfer
request)
SCFRDR2 (SCIF
receive-data-full
transfer request)
Input capture
occurrence
Input capture
occurrence
Input capture
occurrence
Transfer
Source
External*
SCRDR1
External*
SCFRDR2 External*
External*
External*
On-chip
peripheral
Transfer
Destination Bus Mode
SCTDR1
External*
SCFTDR2
External*
On-chip
peripheral
External*
Cycle steal
mode
Cycle steal
mode
Cycle steal
mode
Cycle steal
mode
Burst/cycle
steal mode
Burst/cycle
steal mode
Burst/cycle
steal mode