HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 301

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

7.3
Table 7.2 shows the notation used in the following SH instruction list.
Table 7.2
Item
Instruction
mnemonic
Summary of
operation
Instruction code
Privileged mode
T bit
Note: Scaling (×1, ×2, ×4, or ×8) is executed according to the size of the instruction operand(s).
Instruction Set
Notation Used in Instruction List
Format
OP.Sz SRC, DEST
MSB ↔ LSB
Value of T bit after
instruction execution
Description
OP:
Sz:
SRC:
DEST:
→, ←:
(xx):
M/Q/T:
&:
|:
∧
~:
<<n, >>n: n-bit shift
mmmm: Register number (Rm, FRm)
nnnn:
0000:
0001:
1111:
mmm:
nnn:
000:
001:
111:
mm:
nn:
00:
01:
10:
11:
iiii:
dddd:
“Privileged” means the instruction can only be executed
in privileged mode.
—: No change
:
:
:
Operation code
Source and/or destination operand
SR flag bits
Size
Source
Transfer direction
Memory operand
Logical AND of individual bits
Logical OR of individual bits
Logical exclusive-OR of individual bits
Logical NOT of individual bits
Register number (Rn, FRn)
R0, FR0
R1, FR1
R15, FR15
Register number (DRm, XDm, Rm_BANK)
Register number (DRm, XDm, Rn_BANK)
DR0, XD0, R0_BANK
DR2, XD2, R1_BANK
DR14, XD14, R7_BANK
Register number (FVm)
Register number (FVn)
FV0
FV4
FV8
FV12
Immediate data
Displacement
Rev.7.00 Oct. 10, 2008 Page 215 of 1074
Section 7 Instruction Set
REJ09B0366-0700