HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 231

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

4.7.4
Determination of an exception in a write to an SQ or transfer to external memory (PREF
instruction) is performed as follows according to whether the MMU is on or off. In the SH7750 or
SH7750S, if an exception occurs in an SQ write, the SQ contents may be corrupted. In the
SH7750R, original SQ contents are guaranteed. If an exception occurs in transfer from an SQ to
external memory, the transfer to external memory will be aborted.
• When MMU is on
• When MMU is off
4.7.5
In the SH7750R, a load instruction may be executed in the privileged mode to read the contents of
the SQs from the address range of H'FF001000 to H'FF00103C in the P4 area. Only longword
access is possible.
[31:6]
[5]
[4:2]
[1:0]
Operation is in accordance with the address translation information recorded in the UTLB, and
MMUCR.SQMD. Write type exception judgment is performed for writes to the SQs, and read
type for transfer from the SQs to external memory (PREF instruction), and a TLB miss
exception, protection violation exception, or initial page write exception is generated.
However, if SQ access is enabled, in privileged mode only, by MMUCR.SQMD, an address
error will be flagged in user mode even if address translation is successful.
Operation is in accordance with MMUCR.SQMD.
0: Privileged/user access possible
1: Privileged access possible
If the SQ area is accessed in user mode when MMUCR.SQMD is set to 1, an address error will
be flagged.
SQ Protection
Reading the SQs (SH7750R Only)
: H'FF001000
: 0/1
: LW specification : Specification of longword position in SQ0 or SQ1
: 00
: Store queue specification
: 0: SQ0 specification, 1: SQ1 specification
: Fixed at 0
Rev.7.00 Oct. 10, 2008 Page 145 of 1074
REJ09B0366-0700
Section 4 Caches