HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 665

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

In dual address mode, data corresponding to the size specified by CHCRn.TS is read from the
transfer source in the data read cycle, and, in the data write cycle, it is transferred in two bus
cycles in order to write in the transfer destination the data corresponding to the size specified by
CHCRn.TS. In this process, the transfer data is temporarily stored in the data buffer in the bus
state controller (BSC).
In a transfer between external memories such as that shown in figure 14.7, data is read from
external memory into the BSC's data buffer in the read cycle, then written to the other external
memory in the write cycle. Figure 14.8 shows the timing for this operation. The DACK output
timing is the same as that of CSn in a read or write cycle specified by the CHCRn.AM bit.
Taking the SAR value as the address, data is read from the transfer source module
and stored temporarily in the data buffer in the bus state controller (BSC).
Taking the DAR value as the address, the data stored in the BSC's data buffer is
written to the transfer destination module.
DMAC
DMAC
BSC
BSC
Data buffer
Data buffer
Figure 14.7 Operation in Dual Address Mode
SAR
DAR
SAR
DAR
2nd bus cycle
1st bus cycle
Section 14 Direct Memory Access Controller (DMAC)
Rev.7.00 Oct. 10, 2008 Page 579 of 1074
Transfer destination
Transfer destination
Transfer source
Transfer source
Memory
Memory
module
module
module
module
REJ09B0366-0700