R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 1152

• Manufacturer Part Number: R8A77850BDBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850BDBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

22. Serial I/O with FIFO (SIOF)
22.3.9
SIFCTR is a 16-bit readable/writable register that indicates the area available for the
transmit/receive FIFO transfer.
Rev.1.00 Jan. 10, 2008 Page 1120 of 1658
REJ09B0261-0100
Initial value:
Bit
15 to 13 TFWM[2:0]
12 to 8
R/W:
BIt:
FIFO Control Register (SIFCTR)
Bit Name
TFUA[4:0]
R/W
15
0
TFWM[2:0]
R/W
14
0
R/W
13
0
Initial
Value
000
10000
12
R
1
R/W
R/W
R
11
R
0
TFUA[4:0]
10
R
0
Description
Transmit FIFO Watermark
000: Issue a transfer request when 16 stages of the
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: Issue a transfer request when 12 or more stages
101: Issue a transfer request when 8 or more stages of
110: Issue a transfer request when 4 or more stages of
111: Issue a transfer request when 1 or more stages of
•
•
Transmit FIFO Usable Area
These bits indicate the number of words that can be
transferred by the CPU or DMAC as B'00000 (full) to
B'10000 (empty).
R
9
0
A transfer request to the transmit FIFO is issued by
the TDREQE bit in SISTR.
The transmit FIFO is always used as 16 stages of
the FIFO regardless of these bit settings.
transmit FIFO are empty.
of the transmit FIFO are empty.
the transmit FIFO are empty.
the transmit FIFO are empty.
transmit FIFO are empty. Setting prohibited when
using the DMA transfer.
R
8
0
R/W
7
0
RFWM[2:0]
R/W
6
0
R/W
5
0
R
4
0
R
3
0
RFUA[4:0]
R
2
0
R
1
0
R
0
0