R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 1508
![IC SUPERH MPU ROMLESS 436BGA](/photos/28/62/286211/436-bfbga_sml.jpg)
R8A77850BDBGV#RD0Z
Manufacturer Part Number
R8A77850BDBGV#RD0Z
Description
IC SUPERH MPU ROMLESS 436BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850BDBGV#RD0Z
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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29. User Break Controller (UBC)
29.3.4
1. Table 29.4 shows the relation between the operand sizes specified using the match condition
Table 29.4 Relation between Operand Sizes and Address Bits to Be Compared
2. When the data value is included in the channel 1 match conditions:
3. The operand access accompanying the PREF, OCBP, OCBWB, and OCBI instructions are
Rev.1.00 Jan. 10, 2008 Page 1476 of 1658
REJ09B0261-0100
Selected Operand Size
Quadword
Longword
Word
Byte
Operand size is not included in the
match conditions
setting register (CBR0 or CBR1) and the address bits to be compared for the operand access
cycle break.
The above table means that if address H'00001003 is set in the match address setting register
(CAR0 or CAR1), for example, the match condition is satisfied for the following access cycles
(assuming that all the other conditions are satisfied):
⎯ Longword access to address H'00001000
⎯ Word access to address H'00001002
⎯ Byte access to address H'00001003
If the data value is included in the match conditions, be sure to select the quadword, longword,
word, or byte as the operand size using the operand size select bit (SZ) of the match condition
setting register (CBR1), and also set the match data setting register (CDR1) and the match data
mask setting register (CDMR1). With these settings, the match condition is satisfied when both
of the address and data conditions are satisfied. The data value and mask control for byte
access, word access, and longword access should be set in bits 7 to 0, 15 to 0, and 31 to 0 in
the bits CDR1 and CDMR1, respectively. For quadword access, 64-bit data is divided into the
upper and lower 32-bit data units, and each unit is independently compared with the specified
condition. When either the upper or lower 32-bit data unit satisfies the match condition, the
match condition for the 64-bit data is determined to be satisfied.
access without the data value; therefore, if the data value is included in the match conditions
for these instructions, the match conditions will never be satisfied.
Operand Access Cycle Break
Address Bits to be Compared
Address bits A31 to A3
Address bits A31 to A2
Address bits A31 to A1
Address bits A31 to A0
Address bits A31 to A3 for quadword access
Address bits A31 to A2 for longword access
Address bits A31 to A1 for word access
Address bits A31 to A0 for byte access
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