R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 586

• Manufacturer Part Number: R8A77850BDBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850BDBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

13. PCI Controller (PCIC)
13.2
Table 13.1 shows the pin configuration of the PCIC.
Table 13.1 Signal Descriptions
Rev.1.00 Jan. 10, 2008 Page 554 of 1658
REJ09B0261-0100
Signal Name
D32/AD0/DR0 to
D37/AD5/DR5,
D38/AD6/DG0 to
D43/AD11/DG5,
D44/AD12/DB0 to
D49/AD17/DB5,
D50/AD18 to
D63/AD31
WE7/CBE3 to
WE4/CBE0
PAR
PCICLK/
DCLKIN
PCIFRAME/
VSYNC
TRDY/DISP
IRDY/HSYNC
STOP/CDE
Input/Output Pins
PCI Standard
Signal
AD[31:0]
C/BE[3:0]
PAR
CLK
FRAME
TRDY
IRDY
STOP
I/O
TRI
TRI
TRI
IN
STRI
STRI
STRI
STRI
Description
PCI Address/Data Bus
Address and data buses are multiplexed. In each bus
transaction, an address phase is followed by one or
more data phases.
PCI Command/Byte Enable
Commands and byte enable are multiplexed. These
signals indicate the type of command and byte enable
during the address phase and the data phases
respectively.
PCI Parity
Generates/checks even parity between AD[31:0] to
C/BE[3:0].
PCI Clock
Provides timing for all transactions on the PCI bus.
PCI Frame
Driven by the current initiator, and indicates the start
and duration of a transaction.
PCI Target Ready
Driven by the selected target, and indicates the target
is ready to start and maintain a transaction.
PCI Initiator Ready
Driven by the current bus master. During writing,
indicates that valid data is present on the AD [31:0]
lines. During reading, indicates that the master is ready
to accept data.
PCI Stop
Driven by the selected target drives to stop the current
transaction.