R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 548

• Manufacturer Part Number: R8A77850BDBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850BDBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

12. DDR2-SDRAM Interface (DBSC2)
12.5.3
The following shows an example of the initialization sequence. For detailed information such as
the power supply and timing parameters, please refer to the datasheet for the DDR2-SDRAM
being used.
1. Following the instructions in the datasheet guide for the SDRAM being used, supply the power
2. After the power-on reset has been canceled for the LSI and the CPU has begun operating, the
3. Enter the settings for the SDRAM configuration setting register (DBCONF), the SDRAM
4. DLL settings are entered by writing them to the DDRPAD frequency setting register
5. Write the setting to the DDRPAD DIC, ODT, OCD setting register (DBDICODTOCD). The
6. Writing to the CMD bits in the SDRAM command control register (DBCMDCNT) sets the
7. Writing to the CMD bits in DBCMDCNT issues the PALL command.
8. Writing to the SDRAM mode setting register (DBMRCNT) issues the EMRS(2) command to
9. Writing to DBMRCNT issues the EMRS(1) command to the SDRAM and sets various
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and the reference voltage.
system judges whether the LSI was in power supply backup mode or the normal initialization
sequence (for information on entering settings in power backup mode, please refer to (2)
Recovery from SDRAM Power Supply Backup Mode in section 12.5.10, DDR2-SDRAM
Power Supply Backup Function). If it was an initialization sequence, the software is used to
initiate a wait of at least 100 μs. (An example of how to make the system wait for a specific
interval such as 100 μs can be found in section 12.5.11, Method for Securing Time Required
for Initialization, Self-Refresh Cancellation, etc.)
timing register 0 (DBTR0), the SDRAM timing register 1 (DBTR1), and the SDRAM timing
register 2 (DBTR2).
(DBFREQ).
A. Set DLLRST = 0.
B. Set the frequency of DDRPAD in the FREQ bit.
C. After DLLRST has been set to 1, the time interval of 100 μs that the DLL needs in order to
value written to the register should match the value set in EMRS(1) of the SDRAM.
MCKE signal to the high level (H), and the software is used to have the system wait for at least
400 ns.
the SDRAM. After that, the EMRS(3) command is issued.
parameters in the EMRS(1) register in the DDR2-SDRAM. The values for DIC, ODT, and
OCD should be set to match the DIC bit, ODT bit, and OCD bit settings in the DIC, ODT,
OCD setting registers of DDRPAD.
stabilize is applied through the software. The clock stabilization supply time of 200 μs that
is required for the DDR2-SDRAM to boot, including the wait time described in item 2
above, can be assured.
Initialization Sequence