R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 1502
![IC SUPERH MPU ROMLESS 436BGA](/photos/28/62/286211/436-bfbga_sml.jpg)
R8A77850BDBGV#RD0Z
Manufacturer Part Number
R8A77850BDBGV#RD0Z
Description
IC SUPERH MPU ROMLESS 436BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850BDBGV#RD0Z
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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29. User Break Controller (UBC)
29.2.7
CETR1 is a readable/writable 32-bit register which specifies the number of the channel hits before
a break occurs. A maximum value of 2
included in the match conditions by using the match condition setting register, the value of this
register is decremented by one every time the channel is hit. When the channel is hit after the
register value reaches H'001, a break occurs.
Rev.1.00 Jan. 10, 2008 Page 1470 of 1658
REJ09B0261-0100
Bit
31 to 12 —
11 to 0
Initial value :
Initial value :
R/W:
R/W:
Bit :
Bit :
Bit Name
CET
Execution Count Break Register 1 (CETR1)
31
15
R
R
0
0
30
14
R
R
0
0
Initial
Value
All 0
Undefined R/W
29
13
R
R
0
0
28
12
R
R
0
0
R/W
R
R/W
27
11
R
0
12
R/W
26
10
R
– 1 can be specified. When the execution count value is
0
Description
Reserved
For read/write in this bit, refer to General Precautions on
Handling of Product.
Execution Count
Specifies the execution count to be included in the break
conditions.
R/W
25
R
0
9
R/W
24
R
0
8
R/W
23
R
0
7
R/W
22
R
0
6
CET
R/W
21
R
0
5
R/W
20
R
0
4
R/W
19
R
0
3
R/W
18
R
0
2
R/W
17
R
0
1
R/W
16
R
0
0
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