R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 161
![IC SUPERH MPU ROMLESS 436BGA](/photos/28/62/286211/436-bfbga_sml.jpg)
R8A77850BDBGV#RD0Z
Manufacturer Part Number
R8A77850BDBGV#RD0Z
Description
IC SUPERH MPU ROMLESS 436BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850BDBGV#RD0Z
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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Manufacturer
Quantity
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- Current page: 161 of 1694
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6.2.2
Figure 6.3 shows the bit pattern of a non-number (NaN). A value is NaN in the following case:
• Sign bit: Don't care
• Exponent field: All bits are 1
• Fraction field: At least one bit is 1
The NaN is a signaling NaN (sNaN) if the MSB of the fraction field is 1, and a quiet NaN (qNaN)
if the MSB is 0.
An sNaN is assumed to be the input data in an operation, except the transfer instructions between
registers, FABS, and FNEG, that generates a floating-point value.
• When the EN.V bit in FPSCR is 0, the operation result (output) is a qNaN.
• When the EN.V bit in FPSCR is 1, an invalid operation exception will be generated. In this
Following three instructions are used as transfer instructions between registers.
• FMOV FRm,FRn
• FLDS FRm,FPUL
• FSTS FPUL,FRn
If a qNaN is input in an operation that generates a floating-point value, and an sNaN has not been
input in that operation, the output will always be a qNaN irrespective of the setting of the EN.V bit
in FPSCR. An exception will not be generated in this case.
The qNAN values as operation results are as follows:
• Single-precision qNaN: H'7FBF FFFF
• Double-precision qNaN: H'7FF7 FFFF FFFF FFFF
case, the contents of the operation destination register are unchanged.
Non-Numbers (NaN)
N = 1:sNaN
N = 0:qNaN
31 30
x
11111111
Figure 6.3 Single-Precision NaN Bit Pattern
23 22
Nxxxxxxxxxxxxxxxxxxxxxx
Rev.1.00 Jan. 10, 2008 Page 129 of 1658
6. Floating-Point Unit (FPU)
REJ09B0261-0100
0
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