R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 288

• Manufacturer Part Number: R8A77850BDBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850BDBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

9. On-Chip Memory
9.3
9.3.1
(1)
Instruction fetch access from the CPU is performed via the cache/RAM internal bus. This access
takes more than one cycle.
(2)
Instruction fetch access from the CPU is performed directly via the instruction bus for a given
virtual address. In the case of successive accesses to the same page of IL memory and as long as
no page conflict occurs, the access takes one cycle.
(3)
Instruction fetch access from the CPU is performed via the cache/RAM internal bus, and one
instruction fetch takes more than one cycle.
9.3.2
Note: Operand access is applied for PC relative access (@(disp,pc)).
(1)
Access from the CPU or FPU is performed via the operand bus for a given virtual address. Read
access from the operand bus by virtual address takes one cycle if the access is made successively
to the same page of OL memory and as long as no page conflict occurs. Write access from the
operand bus by virtual address takes one cycle as long as no page conflict occurs.
(2)
Operand access from the CPU and access from the FPU are performed via the cache/RAM internal
bus. Access via the cache/RAM internal bus takes more than one cycle.
Rev.1.00 Jan. 10, 2008 Page 256 of 1658
REJ09B0261-0100
OL Memory
IL Memory
U Memory
OL Memory
IL Memory
Operation
Instruction Fetch Access from the CPU
Operand Access from the CPU and Access from the FPU