DK-DEV-4SGX530N Altera, DK-DEV-4SGX530N Datasheet - Page 10

• Manufacturer Part Number: DK-DEV-4SGX530N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IV GXr
• Type: FPGAr

Specifications of DK-DEV-4SGX530N

• Contents: Board, Cable, Documentation, Power Supply
• For Use With/related Products: Stratix® IV GX
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2714

2–2
Board Overview
Figure 2–1. Overview of the Stratix IV GX FPGA Development Board Features
Table 2–1. Stratix IV GX FPGA Development Board Components (Part 1 of 3)
Stratix IV GX FPGA Development Board Reference Manual
DDR3 x64 Bottom Port
Featured Devices
U13
U31
Configuration, Status, and Setup Elements
SW6
SW4
J8
SW5
D5
Board Reference
HDMI Video Port (J11)
Gigabit Ethernet Port
(U5, U12, U18, U24)
Reset Configuration
Configuration Done
HSMC Port A (J1)
Flash x16 Memory
SDI Video Port
Connector (J7)
Push-Button
USB Type-B
Switch (S1)
LED (D5)
(J3, J5)
(U32)
(J6)
Transceiver TX SMA Connectors
SSRAM x36 Memory (U30)
FPGA
CPLD
JTAG DIP switch
Board Settings DIP switch
JTAG connector
PCI Express DIP switch
Configuration done LED
This section provides an overview of the Stratix IV GX FPGA development board,
including an annotated board image and component descriptions.
provides an overview of the development board features.
Table 2–1
Fan Power Header
CPU Reset Push-button Switch (S2)
Type
describes the components and lists their corresponding board references.
Stratix IV GX FPGA (U13)
PCI Express Edge Connector
EP4SGX230KF40, 1517-pin BGA.
EPM2210GF256, 256-pin BGA.
Enables and disables devices in the JTAG chain.
Controls the Max II CPLD EPM2210 System Controller functions such
as clock enable, power and temperature monitor, as well as voltage
settings for transceivers and SMA clock input control.
Disables embedded blaster (for use with external USB-Blasters).
Controls the PCI Express lane width by connecting prsnt pins
together on the PCI Express edge connector.
Illuminates when the FPGA is configured.
User DIP Switch (SW3)
(J17)
General User Push-button Switches (S3, S4, S5)
Power Monitor Rotary Switch (SW2)
Clock Output SMA Connector (J9)
Clock Input SMA Connector (J14, J15)
Description
Max II CPLD EPM2210 System Controller (U31)
Character LCD (J16)
August 2010 Altera Corporation
Chapter 2: Board Components
Figure 2–1
Board Overview
QDRII+ x18/x18
Top Port 1 (U7)
DC Input Jack (J4)
QDRII+ x18/x18
Top Port 0 (U22)
JTAG Connector
(J8)
DDR3 x16
Top Port (U14)
HSMC Port B
(J2)
Power Switch
(SW1)