DK-DEV-4SGX530N Altera, DK-DEV-4SGX530N Datasheet - Page 70

• Manufacturer Part Number: DK-DEV-4SGX530N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IV GXr
• Type: FPGAr

Specifications of DK-DEV-4SGX530N

• Contents: Board, Cable, Documentation, Power Supply
• For Use With/related Products: Stratix® IV GX
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2714

2–62
Table 2–54. SSRAM Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 3)
Table 2–55. SSRAM Component Reference and Manufacturing Information
Stratix IV GX FPGA Development Board Reference Manual
U30.R1
U30.H11
Board Reference
U30
Board Reference
Flash
Standard synchronous pipelined
SCD, 512K × 36 bit, 250 MHz
Mode
Sleep
Table 2–55
The flash interface consists of a single synchronous flash memory device, providing
64 Mbyte interface with a 16-bit data bus. This device is part of the shared FSM Bus,
which connects to flash memory, SSRAM, and the Max II CPLD EPM2210 System
Controller.
There are two 256 Mbyte die per package with A(25) low selecting the lower die and
A(25) high selecting the upper die. Parameter blocks are 32 K and main blocks are
128 K. The parameters of this device are located at both the top and bottom of the
address space.
This 16-bit data memory interface can sustain burst read operations at up to 52 MHz
for a throughput of 832 Mbps. The write performance is 125 µs for a single word and
440 µs for a 32-word buffer. The erase time is 400 ms for a 32 K parameter block and
1200 ms for a 128 K main block.
Description
Description
lists the SSRAM component reference and manufacturing information.
Schematic Signal Name
ISSI Inc.
Manufacturer
SRAM_MODE
SRAM_ZZ
IS61VPS51236A-250B3
Manufacturing
Part Number
I/O Standard
2.5-V
August 2010 Altera Corporation
Chapter 2: Board Components
(Connects to the MAX II
CPLD EPM2210 System
Stratix IV GX Device
Pin Number
Controller)
Manufacturer
www.issi.com
AJ29
Website
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Memory