DK-DEV-4SGX530N Altera, DK-DEV-4SGX530N Datasheet - Page 42
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DK-DEV-4SGX530N
Manufacturer Part Number
DK-DEV-4SGX530N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IV GXr
Type
FPGAr
Datasheets
1.DK-DEV-4SGX530N.pdf
(57 pages)
2.DK-DEV-4SGX530N.pdf
(84 pages)
3.DK-DEV-4SGX530N.pdf
(1 pages)
Specifications of DK-DEV-4SGX530N
Contents
Board, Cable, Documentation, Power Supply
For Use With/related Products
Stratix® IV GX
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2714
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
2–34
Stratix IV GX FPGA Development Board Reference Manual
f
1
For more information about the HSMC specification such as signaling standards,
signal integrity, compatible connectors, and mechanical information, refer to the
Speed Mezzanine Card (HSMC) Specification
The HSMC connector has a total of 172 pins, including 120 signal pins, 39 power pins,
and 13 ground pins. The ground pins are located between the two rows of signal and
power pins, acting both as a shield and a reference. The HSMC host connector is
based on the 0.5 mm-pitch QSH/QTH family of high-speed, board-to-board
connectors from Samtec. There are three banks in this connector. Bank 1 has every
third pin removed as done in the QSH-DP/QTH-DP series. Bank 2 and bank 3 have
all the pins populated as done in the QSH/QTH series.
Figure 2–11
connector's three banks.
Figure 2–11. HSMC Signal and Bank Diagram
The HSMC interface has programmable bi-directional I/O pins that can be used as
2.5-V LVCMOS, which is 3.3-V LVTTL-compatible. These pins can also be used as
various differential I/O standards including, but not limited to, LVDS, mini-LVDS,
and RSDS with up to 17 full-duplex channels.
As noted in the
single-ended I/O standards are only guaranteed to function when mixed according to
either the generic single-ended pin-out or generic differential pin-out.
shows the bank arrangement of signals with respect to the Samtec
High Speed Mezzanine Card (HSMC) Specification
8 RX Channels CDR
8 TX Channels CDR
CLKIN2, CLKOUT2
CLKIN1, CLKOUT1
CLKIN0, CLKOUT0
D[3:0] + LVDS
D(79.40)
D(39:0)
Bank 2
Bank 3
Bank 1
Power
Power
LVDS
manual.
JTAG
SMB
-or-
-or-
August 2010 Altera Corporation
Chapter 2: Board Components
manual, LVDS and
Components and Interfaces
High