DK-DEV-4SGX530N Altera, DK-DEV-4SGX530N Datasheet - Page 47

• Manufacturer Part Number: DK-DEV-4SGX530N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IV GXr
• Type: FPGAr

Specifications of DK-DEV-4SGX530N

• Contents: Board, Cable, Documentation, Power Supply
• For Use With/related Products: Stratix® IV GX
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2714

Chapter 2: Board Components
Components and Interfaces
Table 2–38. HSMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4)
August 2010 Altera Corporation
J2.16
J2.17
J2.18
J2.19
J2.20
J2.21
J2.22
J2.23
J2.24
J2.25
J2.26
J2.27
J2.28
J2.29
J2.30
J2.31
J2.32
J2.33
J2.34
J2.35
J2.36
J2.37
J2.38
J2.39
J2.40
J2.41
J2.42
J2.43
J2.44
J2.47
J2.48
J2.49
J2.50
J2.53
J2.54
J2.55
J2.56
J2.59
Reference
Board
Transceiver RX bit 4n
Transceiver TX bit 3
Transceiver RX bit 3
Transceiver TX bit 3n
Transceiver RX bit 3n
Transceiver TX bit 2
Transceiver RX bit 2
Transceiver TX bit 2n
Transceiver RX bit 2n
Transceiver TX bit 1
Transceiver RX bit 1
Transceiver TX bit 1n
Transceiver RX bit 1n
Transceiver TX bit 0
Transceiver RX bit 0
Transceiver TX bit 0n
Transceiver RX bit 0n
Management serial data
Management serial clock
JTAG clock signal
JTAG mode select signal
JTAG data output
JTAG data input
Dedicated CMOS clock out
Dedicated CMOS clock in
Dedicated CMOS I/O bit 0
Dedicated CMOS I/O bit 1
Dedicated CMOS I/O bit 2
Dedicated CMOS I/O bit 3
LVDS TX bit 0 or CMOS bit 4
LVDS RX bit 0 or CMOS bit 5
LVDS TX bit 0n or CMOS bit 6
LVDS RX bit 0n or CMOS bit 7
LVDS TX bit 1 or CMOS bit 8
LVDS RX bit 1 or CMOS bit 9
LVDS TX bit 1n or CMOS bit 10
LVDS RX bit 1n or CMOS bit 11
LVDS TX bit 2 or CMOS bit 12
Description
Schematic Signal
FPGA_JTAG_TCK
FPGA_JTAG_TMS
HSMB_JTAG_TDO
HSMB_JTAG_TDI
HSMB_CLK_OUT0
HSMB_CLK_IN0
HSMB_TX_D_P0
HSMB_RX_D_P0
HSMB_TX_D_N0
HSMB_RX_D_N0
HSMB_TX_D_P1
HSMB_RX_D_P1
HSMB_TX_D_N1
HSMB_RX_D_N1
HSMB_TX_D_P2
HSMB_RX_N4
HSMB_RX_N3
HSMB_RX_N2
HSMB_RX_N1
HSMB_RX_N0
HSMB_RX_P3
HSMB_TX_N3
HSMB_RX_P2
HSMB_TX_N2
HSMB_RX_P1
HSMB_TX_N1
HSMB_RX_P0
HSMB_TX_N0
HSMB_TX_P3
HSMB_TX_P2
HSMB_TX_P1
HSMB_TX_P0
HSMB_SDA
HSMB_SCL
HSMB_D0
HSMB_D1
HSMB_D2
HSMB_D3
Name
Stratix IV GX FPGA Development Board Reference Manual
LVDS or 2.5-V
I/O Standard
1.4-V PCML
2.5-V
Stratix IV GX
Pin Number
Device
AN10
AF29
AB27
AK29
AA35
AP10
M36
M37
AW8
W12
W11
B36
C38
B37
C39
D36
E38
D37
E39
K36
L38
K37
L39
N38
N39
AV8
V12
V11
V10
W8
W7
C1
—
—
—
—
V6
U5
2–39